A 0.0129 mm2 DPLL With 1.6~2.0 ps RMS Period Jitter and 0.25-to-2.7 GHz Tunable DCO Frequency Range in 55-nm CMOS

Abstract

The proposed digital phase locked loop uses a time-to-digital converter with associated simple algorithm to improve jitter performance. The wide frequency tuning is achieved through three different loop delay control schemes of the digital controlled oscillator (DCO). Verified in GLOBALFOUNDRIES 55 nm LPX process, the chip occupies 0.0129 mm2, achieves a wide range of 250 MHz to 2.7 GHz, and consumes only 1.1 mW when DCO’s frequency is 500 MHz. The phase locked loop output clock jitter is around 1.6–2.0 ps.