Digital Power Amplifier Research Articles

A Multimode Multi-Efficiency-Peak Digital Power Amplifier

A 30.0-dBm polar digital power amplifier (PA) is implemented based on a switched-capacitor PA (SCPA) and multiple efficiency-enhancement techniques, such as Class-G, Doherty, and time interleaving (TI). The PA demonstrates six efficiency peaks and seamless efficiency curves between the peaks in the power back-off (PBO) region with the three efficiencyenhancement techniques. For the implementation of the efficient and linear Class-G technique, a linear single-supply current-reuse Class-G switch is proposed. It realizes a Class-G operation without any additional dedicated supply voltages, resulting in enhanced efficiency and reduced cost for an external power management unit (PMU). A local oscillator (LO) signal restoration technique is proposed to reduce the area and power consumption for the LO signal distribution. The prototype SCPA, fabricated in a 65-nm CMOS, generates 30-dBm peak output power (POUT) at 2.4 GHz and achieves drain efficiency (DE) (normalized DE) of 40.2% (100%), 37.9% (94.3%), 38.8% (96.3%), 36.3% (90.2%), 29.4% (73.0%), and 19.7% (48.9%) at 0-, 2.5-, 6-, 8.5-, 12-, and 18-dB PBOs, respectively. It achieves less than ±1° amplitude modulation (AM)-phase modulation (PM) distortion with a continuous-wave (CW) signal. It also demonstrates error vector magnitude (EVM) of -41.7 dB (-44.5 dB) and DE of 30.3% (36.2%) at an average output power of 19.1 dBm (23.2 dBm) for a 10-MHz 64-quadrature AM (QAM) orthogonal frequency-division multiplexing (OFDM) signal with a 10.9-dB peak-to-average power ratio (PAPR) (10-MHz single-carrier 1024-QAM signal with 6.8-dB PAPR).

1.2–2.8-GHz 32.4-dBm Digital Power Amplifier With Balance-Compensated Matching Network

In this letter, a wideband watt-level digital power amplifier (DPA) with a balance-compensated matching network is proposed for polar transmitters. The balance response of the differential to the single-ended transformer is enhanced by a series-loaded compensation capacitor, which leads to the improvement of the DPA efficiency. To verify the mechanisms, a prototype DPA is fabricated in conventional 40-nm CMOS technology. The proposed DPA operates over 1.2–2.8 GHz and exhibits a peak output power of 32.4 dBm at 2 GHz and a peak drain efficiency of 53.8% at 1.8 GHz. It supports 50-MHz 64-quadratic-amplitude modulation (QAM) with average output power ( $P_{\text {avg}}$ ) of 25.37 dBm, error vector magnitude (EVM) of −26.97 dB, adjacent channel power ratio (ACPR) of −29.61 dBc, and 10-MHz 1024-QAM with $P_{\text {avg}}$ of 22.14 dBm, EVM of −35.75 dB, and ACPR of −35.37 dBc, respectively.

Modified indirect learning applied to neural network-based pre-distortion of a concurrent dual-band CMOS power amplifier

Current radio communication systems that adopt amplitude and phase modulations demand high linearity and high efficiency. The cascade connection between digital baseband pre-distorter (DPD) and power amplifier (PA) can be a cost-effective solution to guarantee the required linearity without compromising the efficiency. In the design of a DPD for a single band PA, direct learning can be used to extract the pre-inverse parameters or, alternatively, indirect learning can be employed by exchanging the position of the system during the identification procedure to avoid the necessity of a PA model within a closed-loop process. The performance of direct learning is substantially dependent on the accuracy of the behavioral model that replaces the PA. Furthermore, in a practical environment where only an approximation to the inverse is achieved, the linearization capability of the indirect learning is affected by shifting the post-inverse placed after the PA to a pre-inverse located before the PA. For concurrent dual-band PAs, an additional advantage of the indirect approach is that the post-inverse identifications for each band are completely independent of each other. In an authors’ previous work, a comparative analysis between the two learning architectures applied to the linearization of concurrent dual-band PAs was performed based on DPDs modeled by polynomials with memory. This work contributions are the extension of such comparative analysis to DPDs modeled by artificial neural networks, the development of complex-valued three-layer perceptrons suitable for concurrent-dual band DPDs and the introduction of a modified indirect approach to improve the accuracy of previous direct and indirect learnings. Spectre-RF transient simulations are performed in the circuit-under-test described by a wideband 130 nm CMOS PA concurrently stimulated by 2.4 GHz Wi-Fi and 3.5 GHz LTE signals. Reported simulation results show that, in a comparison with the previous direct and indirect learnings with similar output mean powers of about 60 mW, the modified indirect approach provides a superior linearity performance. The modified indirect learning reduces the error vector magnitude (EVM) metric to 0.87% and 1.13% for Wi-Fi and LTE bands, respectively, whereas the indirect and direct learnings achieve EVM equal to or larger than 1.05% and 1.49% for Wi-Fi and LTE bands, respectively.

Radio & Wireless Week 2021 [From the Guest Editor's Desk

This focus issue of IEEE Microwave Magazine contains columns on topics being covered during IEEE Radio & Wireless Week 2021 (RWW 2021) and five overview feature articles dedicated to themes that represent the scope and purpose of the different subconferences within RWW. The five feature articles have been prepared by highly renowned authors in their research fields and address several timely technical topics, such as digital predistortion (DPD) in power amplifiers (PAs); integrated digital power amplifiers (DPAs) and transmitters; reflectionless filtering devices; emerging inkjet and 3D printing fabrication techniques for sensing, communication, and empowering tasks in modern Internet of Things (IoT) modules; and advanced receiver architectures with multiband, multifunction, and multimode operational capabilities.

A Fully Integrated 27-dBm Dual-Band All-Digital Polar Transmitter Supporting 160 MHz for Wi-Fi 6 Applications

This work presents a dual-band polar digital transmitter (P-DTX) based on a digitally controlled two-point edge interpolation digital-to-time converter, which is capable of supporting Wi-Fi 6 applications. The proposed P-DTX is fabricated in a standard 28-nm CMOS process. The 2.5/5GHz digital power amplifiers (DPAs) reach a maximum power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</sub> )/power efficiency (PE) of 27 dBm/53% and 27dBm/37%, respectively. The transmitter meets an error vector magnitude (EVM)/DPA PE/total TX power dissipation of -30.5 dB/33%/532 mW for the low band and -29 dB/26%/718 mW for the high band at 6-dB backoff (dBBO) from PMAX. An EVM as low as -40 dB is achieved using digital pre-distortion at 7-8 dBBO, for 20-160-MHz signal bandwidths, thus demonstrating MCS11 1024-QAM OFDM Wi-Fi 6 operation.

An Energy-Efficient 10-Gb/s CMOS Millimeter-Wave Transceiver With Direct-Modulation Digital Transmitter and I/Q Phase-Coupled Frequency Synthesizer

A fully integrated energy-efficient 10-Gb/s millimeter-wave transceiver with direct-modulation digital transmitter (TX) and I/ Q phase-coupled frequency synthesizer in 65 nm CMOS is presented. The transceiver consists of a direct-conversion receiver (RX), a digital TX with on-chip QPSK modulation, and a quadrature local-oscillation (LO) generation network with a 20-GHz phase-locked loop (PLL) frequency synthesizer. A T/R switch is integrated to interface with an E-shaped patch antenna. The QPSK modulation is directly realized in the I/ Q digital power amplifier (DPA), which simplifies the TX complexity and reduces the power consumption. A 20-GHz sub-sampling PLL (SSPLL) and a quadrature phased-coupled injection-locked oscillator (QILO) are integrated on-chip to generate 60-GHz quadrature LO signals. The QILO utilizes in-phase coupling technique to improve the LO I/ Q matching and phase noise performance. The RX achieves 7.1-dB noise figure (NF) and 25- to 47-dB dynamic gain range. The LO phase noise measured at the TX output is -115.6 dBc/Hz at 10 MHz offset from 60 GHz carrier. The measured error vector magnitude (EVM) of the TX is -23.9 dB for 10-Gb/s QPSK signals at 7-dBm output power. The EVM of the over-the-air (OTA) modulation-demodulation system is -13.8 dB for 10-Gb/s QPSK signals. The transceiver achieves the 10-Gb/s data rate while consuming 340.4 mW. The energy efficiency is 34 pJ/bit. This work demonstrates the fully functional wireless link based on the proposed mm-wave transceiver, which highlights the possibility of energy-efficient solution for future high throughputs mm-wave wireless systems.

A Broadband Switched-Transformer Digital Power Amplifier for Deep Back-Off Efficiency Enhancement

This article presents a switched-transformer-based polar Doherty digital power amplifier (DPA) for deep back-off efficiency enhancement. A single-transformer-footprint parallel-combining transformer (PCT) power combiner is introduced for 1.3-3.5-GHz wide frequency coverage, dynamic load modulation at 0-/6-/12-/18-dB power back-off (PBO) levels, and an ultracompact die size. Implemented in 40-nm CMOS, the DPA is powered by a 1.1-V supply and only occupies 0.7 × 1.15 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip area. It achieves 21.4-dBm peak power with the power added efficiencies (PAEs) of 31.3%, 27.7%, 16.6%, and 7.7% for 0-/6-/12-/18-dB PBOs at 1.5 GHz. With 20-MHz 64QAM long term evolution (LTE) signal, the DPA achieves P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">avg</sub> of 15.2 dBm and the average PAE of 25.3% with -32.5-dB error vector magnitude (EVM) at 1.5 GHz. Moreover, for 20-MHz 64 QAM WLAN signal, Pavg of 14.7 dBm with the average PAE of 20.1% is obtained with - 25-dB EVM at 2.4 GHz.

A 3-bit load-pulling digital power amplifier

AbstractA radio frequency (RF) 3-bit digital power amplifier (DPA) is described in this paper. It consists of three RF amplifiers connected at their outputs with a transmission line (TL) network. The three amplifiers are designed for different output powers (POUT). The TL network allows them to load-pull one other to achieve eight different amplitude states by alternatively enabling and disabling the amplifiers via their gate bias. A prototype was designed in the National Instruments' Microwave Office (MWO) for 500 MHz with the aid of a genetic algorithm to optimize the TL network for all seven active (on-) states. The optimizer efficiencies goals were based on data derived from load-pull simulation. The POUT goals were based on a 1 Vrms step-size. In simulation, ≥50% efficiency was achieved at all on-states with 29.7 dBm peak POUT. A practical prototype based on the simulation achieved an efficiency of ≥40% over all seven on-states. A peak POUT of 28.9 dBm was achieved, with the lowest state at 22.4 dBm.

GaN digital microwave outphasing PA

AbstractThis paper presents a novel GaN-based digital outphasing power amplifier (PA) for the 800 MHz range. The PA reaches a maximum output power of 5.8 W at 30 V final-stage (FS) drain supply voltage. A novel output combiner circuit is used and efficiency is improved by resonant commutation of the FSs and optimized driver circuits for the two GaN push-pull FSs. 3D electromagnetic simulation of output network has been conducted to extract an equivalent circuit model and to access full information in terms of functionality and broadband impedance characteristics for optimized outphasing operation in the final design. Measured total efficiencies (ηtot) of 59 and 25% at 0 and 10 dB power back-off are achieved, respectively, fitting the simulation quite well. The proposed digital outphasing module is a promising candidate for fully digitized base-station architectures in future wireless communications.

Analysis and Design of a Polar Digitally Modulated CMOS PA Based on Switched Constant-Current

Typical polar digital power amplifiers (DPAs) employ unit-cells operated in class-E or D−1, denoting a switched-resistance operation which degrades linearity. Besides introducing higher demand on digital predistortion (DPD), it also requires extra quantization bits, impacting the overall efficiency and system complexity. To address this, the present work makes use of an optimized constant-current cascode unit-cell which is combined with reduced conduction angle to achieve linear and efficient operation, while minimizing the effort on DPD and/or calibration. A design strategy is developed which focuses on the cascode bias voltage and transistor relative dimensions as design parameters, allowing cascode efficiency optimization without compromising linearity or reliability. A single-ended polar switched constant-current DPA is implemented in 180-nm standard CMOS. Continuous-wave measurements performed at 800 MHz demonstrate an output power of 24 dBm with a PAE of 47%. The DPA dynamic behavior was tested with a 64-QAM signal with 10 MS/s, achieving an average PAE of 20.9% with a peak-to-average power ratio (PAPR) of 8.7 dB and adjacent-channel leakage ratio (ACLR) = 40.34 dB. These results demonstrate comparable performance with the prior art while using only 6-bits clocked at 100 MHz baseband sampling frequency.

A CMOS 1.2-V Hybrid Current- and Voltage-Mode Three-Way Digital Doherty PA With Built-In Phase Nonlinearity Compensation

This article presents a fully integrated hybrid current- and voltage-mode three-way digital Doherty power amplifier (PA) in CMOS using a single supply with builtin large-signal phase nonlinearity compensation. The nonlinear phase responses in both current-mode digital PA (C-DPA) and voltage-mode digital PA (V-DPA) are theoretically analyzed, which are further leveraged to achieve the PA nonlinear phase compensation. To the best of our knowledge, it is the first time the amplitude modulation (AM)-phase modulation (PM) response in V-DPA is explained in detail. The PA exploits the lagging AM-PM distortion of C-DPA and leading AM-PM distortion of V-DPAs, resulting in built-in large-signal phase nonlinearity cancellation without phase pre-distortion. Moreover, the transformer-based Doherty output network provides active load modulation to both C-DPA and V-DPA, achieving a three-way Doherty PA for deep power back-off (PBO) efficiency enhancement without supply modulation. Finally, the 1.2-V single power supply for PA power cells and input drivers reduces supply complexity. As a proof-of-concept, the hybrid three-way digital Doherty PA is implemented in a 45-nm CMOS SOI process. The measurements show a 38.5% peak drain efficiency (DE), 22.4-dBm saturated output power (Psat), and 32.1%/18.7% DE at 3.4-/9.3-dB PBO, achieving ×1.25/×1.46 PBO efficiency enhancement over idealistic class-B PA PBO efficiency at 2.3 GHz. The measured AM-PM distortion is 4.7° which is state-of-the-art among DPAs with PBO efficiency enhancement. The hybrid digital Doherty PA supports 40-/10-MSym/s 64-quadrature amplitude modulation (QAM)/256-QAM at 15.3-/15.2-dBm average output power and 24.7%/23.2% average PA DE while maintaining error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR) lower than -32/-32.1 dB and -30.6/-28.9 dBc without phase pre-distortion.

A Super-Resolution Mixed-Signal Doherty Power Amplifier for Simultaneous Linearity and Efficiency Enhancement

This article presents a mixed-signal Doherty power amplifier (MSDPA) architecture for simultaneous linearity and efficiency enhancement. The MSDPA comprises one analog power amplifier (PA) as the main PA and one binary-weighted digital PA as the auxiliary PA. The MSDPA input is a generic envelope-varying complex-modulated signal. Based on the realtime amplitude-modulated (AM) envelope, auxiliary digital PA weightings are dynamically turned-on to perform optimum Doherty load modulation for superior linearity and back-off efficiency. Moreover, quantization noise is largely suppressed by the mixed-signal Doherty operation and nonuniform quantization (NUQ), while spectral images are substantially reduced by the quasi-first-order hold (quasi-FOH) operation, which together achieves super-resolution over conventional digital PAs; this makes the MSDPA conducive to millimeter-wave (mm-Wave) or compound PA designs by obviating the need for a large effective number of bits (ENOB) on AM digital controls. As a proof of concept, a 3-bit MSDPA is implemented at 27 GHz in a 45-nm silicon-on-insulator (SOI) CMOS process. The prototype PA achieves 40.1% peak power-added efficiency (PAE), 23.3-dBm saturated output power (Psat), and 39.4% PAE for 22.4-dBm P1dB at 27 GHz in continuous-wave (CW) measurements. The PAE at 6-dB power back-off (PBO) is 33.1%, which corresponds to a 1.68× improvement over a normalized Class-B PA. With only three control bits, the MSDPA PA supports a 12-Gb/s 64-QAM signal at -24.5-dB rms error vector magnitude (EVM) and average Pout/PAE of +15.6 dBm/27.8% without digital predistortion (DPD).

A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier

This article presents a multi-subharmonic switching (SHS) digital power amplifier (PA) architecture for enhancing power back-off (PBO) efficiency while achieving watt-level output power. The proposed phase-interleaved architecture provides the inherent cancellation of the subharmonic components in the PBO region, alleviating the burden of the matching network. The proposed multi-SHS scheme can be further combined with a class-G operation to create a greater number of efficiency peaks in the PBO region. A transformer-based, three-way power combiner and a triple-stacking class-D driver are utilized to obtain watt-level output power. The proof-of-concept PA prototype is implemented with a switched-capacitor PA (SCPA) architecture in 65-nm CMOS and achieved 30-dBm peak power at 1.9 GHz, with 45.9%/41.3%/35.3%/32.2%/24.2% drain efficiency located at 0-, -3.5-, -7.0-, -9.5-, and -12-dB PBO, respectively. The average efficiency was 31.4% in real-time operation with a 7.2-dB peak-to-average power ratio (PAPR) modulated signal.

A Highly Linear Wideband Polar Class-E CMOS Digital Doherty Power Amplifier

This article presents the first application of a digital-intensive intrinsically linear digitally controlled class-E technique in a Doherty configuration. By careful nonlinear segmentation and multiphase RF-clocking along with overdrive-voltage control and automatic duty-cycle correction, it is shown that even the nonlinearities related to Doherty operation can be fully handled by the underlying design such that digital predistorion (DPD) can be, in principle, omitted. The nonlinearity behavior of the whole digital Doherty power amplifier (PA) is analyzed, and closed-form equations are given to predict the AM-AM and AM-phase modulation (PM) curves. In addition, time/phase mismatch between the peak and main branches and the AM and PM signals is accurately compensated. In order to achieve the maximum intrinsic linearity, two separate chips with the same architecture, but different design parameters, are fabricated as the main and peak amplifiers in 40-nm bulk CMOS. To achieve a large RF bandwidth and high passive combiner efficiency, a differential low-loss, wideband Marchand balun-based Doherty power combiner, implemented using reentrant coupled lines with independent second-harmonic control is proposed, and together with the matching network is fabricated on a two-layer PCB. The measured peak/6-dB power backoff P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> , drain efficiency/power-added efficiency at 2.4 GHz are 17.5 dBm/12.2 dBm, 57%/52% and 36%/25% with VDD main/peak = 0.6 V/0.7 V. Measured results without using DPD show -41-dBc adjacent channel power ratio (ACPR) and -36-dB error vector magnitude (EVM) for a 16-MHz OFDM signal at 2.5 GHz. By using DPD, the measured ACPR and EVM of a 16-MHz /32-MHz OFDM signals are -52 dBc/-48 dBc and -50 dB/-48 dB, respectively.

A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling Mitigation

In this paper, we propose a sub-gigahertz transmitter (TX) with a physically merged digitally controlled oscillator (DCO) and digital power amplifier (DPA). The matching transformer of single-ended DPA is placed inside the DCO transformer to save ~50% of area. The resulting DCO pulling is compensated via a feedback path and an inter-winding cancellation capacitor suppresses the second harmonic. Fabricated in 16-nm FinFET CMOS, the DPA reaches 51% efficiency at 11-dBm output with < −55-dBc HD2. The 1.8-GHz DCO exhibits −116-dBc/Hz phase noise (PN) at 1-MHz offset and draws 195 uW from 0.3-V supply. The error vector magnitude measured with a 2-MHz 64-Quadratic amplitude modulation (QAM) orthogonal frequency division multiplexing signal at 5-dBm average power is 3.7%.

A Compact Dual-Band Digital Polar Doherty Power Amplifier Using Parallel-Combining Transformer

This paper presents a dual-band high-power digital polar Doherty power amplifier (PA). A current-mode parallel-combining transformer (PCT) power combiner is introduced for Doherty operation, which realizes simultaneous dual-band coverage, high output power, and backoff efficiency enhancement with an ultra-compact single-transformer footprint. The PA is implemented in 55-nm CMOS and occupies 1.11 mm2 die area. It achieves 28.9-dBm peak $P_{\mathrm {out}}$ with 36.8% PAE in low band (LB) and 27.0-dBm peak $P_{\mathrm {out}}$ with 25.4% PAE in high band (HB). For 12-subcarrier 180-kHz bandwidth cellular narrowband Internet-of-Things (NB-IoT) signals, the peak $P_{\mathrm {avg}}$ of 24.4 dBm with average PAE of 29.5% at 850 MHz and the peak $P_{\mathrm {avg}}$ of 23.0 dBm with average PAE of 17.9% at 1.7 GHz are obtained with −21.6-dB error vector magnitude (EVM). Moreover, the PA achieves 20.8-dBm $P_{\mathrm {avg}}$ , 22.7% average PAE, and −30.5-dB EVM for 20-MHz 256-QAM WLAN signal.

A Fully Integrated Bluetooth Low-Energy Transceiver with Integrated Single Pole Double Throw and Power Management Unit for IoT Sensors.

This paper presents a low power Gaussian Frequency-Shift Keying (GFSK) transceiver (TRX) with high efficiency power management unit and integrated Single-Pole Double-Throw switch for Bluetooth low energy application. Receiver (RX) is implemented with the RF front-end with an inductor-less low-noise transconductance amplifier and 25% duty-cycle current-driven passive mixers, and low-IF baseband analog with a complex Band Pass Filter(BPF). A transmitter (TX) employs an analog phase-locked loop (PLL) with one-point GFSK modulation and class-D digital Power Amplifier (PA) to reduce current consumption. In the analog PLL, low power Voltage Controlled Oscillator (VCO) is designed and the automatic bandwidth calibration is proposed to optimize bandwidth, settling time, and phase noise by adjusting the charge pump current, VCO gain, and resistor and capacitor values of the loop filter. The Analog Digital Converter (ADC) adopts straightforward architecture to reduce current consumption. The DC-DC buck converter operates by automatically selecting an optimum mode among triple modes, Pulse Width Modulation (PWM), Pulse Frequency Modulation (PFM), and retention, depending on load current. The TRX is implemented using 1P6M 55-nm Complementary Metal–Oxide–Semiconductor (CMOS) technology and the die area is 1.79 mm2. TRX consumes 5 mW on RX and 6 mW on the TX when PA is 0-dBm. Measured sensitivity of RX is −95 dBm at 2.44 GHz. Efficiency of the DC-DC buck converter is over 89% when the load current is higher than 2.5 mA in the PWM mode. Quiescent current consumption is 400 nA from a supply voltage of 3 V in the retention mode.

Highly compact GaN-based all-digital transmitter chain including SPDT T/Rx switch for massive MIMO applications

AbstractThis paper presents a fully digital transmitter chain from baseband to antenna, including a modulator, two truly digital (i.e. fully switched) microwave power amplifiers and a transmit/receive switch. Both, amplifier and switch monolithic microwave integrated circuits were implemented in a GaN HEMT process. The novel amplifier design provides greatly reduced complexity, needing only three voltage sources. Measurements were conducted using 5, 20, and 100 MHz wide baseband signals. Carrier frequencies cover the 900 and 2000 MHz bands. For the 5 MHz BB signal an ACLR of over 52 dB is reached, fulfilling the 3GPP specs for base station use while still maintaining a final-stage drain efficiency of 46% at 6.5 dB peak to average power ratio. Full-scale output power at 30 V supply voltage was measured to exceed 3 W at 80% drain efficiency. Further features of this digital amplifier approach include small form factor and frequency agility, making it an ideal candidate for software defined radio.

A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With −41.3-dB EVM at 1024 QAM in 28-nm CMOS

We present a subsampling polar transmitter (SSPTX) in 28-nm CMOS that consists of a low-noise phase modulating (PM) digital subsampling phase-locked loop (PLL) and a harmonic rejection mixed (HRM) inverse-class-D ( $\mathrm {D}^{-1}$ ) digital power amplifier (DPA) for amplitude modulation (AM). The DPA is, unlike in a typical polar transmitter (TX), placed within the PLL and the phase-error detection happens directly at the DPA output. The subsampling polar TX thus becomes sensitive not only to phase errors but also to modulation amplitude. That feature enables AM–AM and PM–PM distortion to be detected and cancelled digitally in the background, while the transmitter operates normally. Moreover, the AM–PM cross distortion is filtered by the loop itself. The chip operates from a 0.9-V supply at 5.5 GHz with 2.5 MHz BW (1024 QAM) with average 1.1-dBm output power and total power consumption of 50 mW.

A Subharmonic Switching Digital Power Amplifier for Power Back-Off Efficiency Enhancement

This paper presents a subharmonic switching (SHS) digital power amplifier (PA) architecture that enhances power efficiency in the power back-off (PBO) region. The proposed technique can be combined with the class-G operation. By using either SHS or dual-power supply switching, it can provide several peak efficiency points, located at 0, -3.5, -9.5, and, -13 dB PBO. By judiciously choosing the optimal operation mode between SHS and dual supplies for each PA cell at different output power levels, we can further improve the efficiency between peaks. The SHS PA prototype is implemented with a switched-capacitor PA (SCPA) architecture in 65-nm CMOS to validate the effectiveness of the proposed technique, which achieves a 26.8-dBm peak output power with a 49.3% peak drain efficiency (DE) at 2.25 GHz and a 27% DE at -13-dB PBO.