Abstract
In this letter, a wideband watt-level digital power amplifier (DPA) with a balance-compensated matching network is proposed for polar transmitters. The balance response of the differential to the single-ended transformer is enhanced by a series-loaded compensation capacitor, which leads to the improvement of the DPA efficiency. To verify the mechanisms, a prototype DPA is fabricated in conventional 40-nm CMOS technology. The proposed DPA operates over 1.2–2.8 GHz and exhibits a peak output power of 32.4 dBm at 2 GHz and a peak drain efficiency of 53.8% at 1.8 GHz. It supports 50-MHz 64-quadratic-amplitude modulation (QAM) with average output power ( $P_{\text {avg}}$ ) of 25.37 dBm, error vector magnitude (EVM) of −26.97 dB, adjacent channel power ratio (ACPR) of −29.61 dBc, and 10-MHz 1024-QAM with $P_{\text {avg}}$ of 22.14 dBm, EVM of −35.75 dB, and ACPR of −35.37 dBc, respectively.
Highlights
W ITH the ever-development of wireless communication, power amplifiers (PAs) with high power, high efficiency, low supply, and low cost are dramatically demanded
A 1.2–2.8-GHz watt-level digital power amplifier (DPA) with a balancecompensated matching network is proposed. Such matching topology consists of a 4-to-1 transformer with a compensated series-loaded capacitor, which enhances the output power and efficiency, simultaneously
The asymmetry of differential to single-ended transformer shows a significant effect on the efficiency and output power of PAs, especially for the large impedance transformation ratio [22]–[24]
Summary
W ITH the ever-development of wireless communication, power amplifiers (PAs) with high power, high efficiency, low supply, and low cost are dramatically demanded. The system efficiency and integration level of conventional TX are relatively low. Compared with analog PAs, digital PAs (DPAs) [7]–[16] exhibit enhanced efficiency and medium output power. To implement watt-level DPAs, topologies of voltage-combining [17], [18] and currentcombining [19]–[21] are developed. A 1.2–2.8-GHz watt-level DPA with a balancecompensated matching network is proposed. Such matching topology consists of a 4-to-1 transformer with a compensated series-loaded capacitor, which enhances the output power and efficiency, simultaneously. A prototype DPA is implemented and fabricated using a conventional 40-nm CMOS technology, which exhibits 32.4-dBm peak output power and 53.8% peak drain efficiency (DE) under a 1.1-/2.5-V supply
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
