Digital Power Amplifier Research Articles

Robust Fractional Order Memory Polynomial Based Pre-Distorter

In this paper, a robust fractional order memory polynomial pre-distorter with two novel schemes to conduct digital base-band power amplifier pre-distortion is proposed. For the first scheme, fractional order terms are included in the conventional memory polynomial containing the odd and even order polynomial terms, which is called Scheme One. The second scheme, called Scheme Two, simply replaces even order polynomial terms with fractional order polynomial terms to improve the linear performance of power amplifiers. The mathematical expressions for these two schemes are derived. The computer simulations and numerical analysis show that, compared with the conventional pre-distortion methods, 11dB and 8.5dB more out-of-band suppression gain can be obtained by Scheme One and Scheme Two, respectively. Corresponding FPGA realization shows that the two schemes are cost-effective in terms of hardware resources.

An Energy-Efficient All-Digital UWB Transmitter Employing Dual Capacitively-Coupled Pulse-Shaping Drivers

This paper presents an all-digital, non-coherent, pulsed-UWB transmitter. By exploiting relaxed center frequency tolerances in non-coherent wideband communication, the transmitter synthesizes UWB pulses from an energy-efficient, single-ended digital ring oscillator. Dual capacitively coupled digital power amplifiers (PAs) are used in tandem to attenuate low frequency content typically associated with single-ended digital circuits driving single-ended antennas. Furthermore, four level digital pulse shaping is employed to attenuate RF sidelobes, resulting in FCC compliant operation in the 3.5, 4.0, and 4.5 GHz IEEE 802.15.4a bands without the use of any off-chip filters or large passive components. The transmitter is fabricated in a 90 nm CMOS process and occupies a core area of 0.07 mm2 . The entirely digital architecture consumes zero static bias current, resulting in an energy efficiency of 17.5 pJ/pulse at data rates up to 15.6 Mb/s.

Audio power amplifier IC and audio system provided with the same

An audio power amplifier IC, which can suppress audio quality deterioration due to reference clock frequency, and an audio system provided with the audio power amplifier IC. The audio power amplifier IC is provided with a clock generating circuit (10) for generating an internal clock; a clock terminal (CLK) for performing internal clock output or external clock input; a clock selecting circuit (11) which selects either the internal clock or the external clock as the reference clock (BCLK); a first audio signal input terminal (IN1) to which a first audio signal (Lin) is inputted; and a first digital power amplifier circuit (51) which outputs a pulse synchronized with the reference clock (BCLK) by performing pulse modulation to the first audio signal (Lin) based on the reference clock (BCLK).

Two-dimensional indexing polynomial-based pre-distorter for power amplifiers with memory effects

An improved segmented polynomial-based pre-distortion method and a novel memory polynomial-based pre-distortion method with two-dimensional indexing are proposed in digital baseband power amplifier pre-distortion systems. Through computer simulations and corresponding analysis, the feasibility and reliability of the proposed methods are verified with three different polynomial formats in the evaluation of relative mean square error, the convergence speed, the random access memory storage units and the power spectral density.

Narrow Pulse Elimination PWM for Multilevel Digital Audio Power Amplifiers Using Two Cascaded H-Bridges as a Nine-Level Converter

This paper presents a methodology to reduce total harmonic distortion (THD) in digital audio power amplifiers, using two new approaches: 1) a multilevel converter made of two cascaded full-bridges, with suitable power supplies to operate as a nine-level hybrid type converter and 2) a new pulsewidth modulation (PWM) technique called narrow pulse elimination (NPE) PWM. The proposed nine-level converter uses only eight MOSFETs. Unlike conventional PWM, the NPE PWM does not generate excessively narrow pulses, so that power semiconductors nonideal delays and switching times are still negligible. Therefore, the nine-level output voltage THD, mostly introduced in the power stage, is strongly reduced. With the NPE technique, the resolution of the generated PWM is no longer limited by the switching speed of the output switches, but only by the frequency of digital processing circuit. Simulation and experimental results from a laboratory prototype are presented in order to show the effectiveness of the proposed approaches

Controller for digital audio power amplifier with bit stream input

A new controller for a digital audio amplifier with bit stream input is proposed. The proposed controller has excellent features such as wide error correction range and no limitation on the modulation index. The controller is implemented in the half-bridge class-D amplifier and performance is verified through experiments.

Neural network modeling and identification of nonlinear channels with memory: algorithms, applications, and analytic models

This paper proposes a neural network (NN) approach for modeling nonlinear channels with memory. Two main examples are given: (1) modeling digital satellite channels and (2) modeling solid-state power amplifiers (SSPAs). NN models provide good generalization performance (in terms of output signal-to-error ratio). NN modeling of digital satellite channels allows the characterization of each channel component. Neural net models represent the SSPA as a system composed of a linear complex filter followed by a nonlinear memoryless neural net followed by a linear complex filter. If the new algorithms are to be used in real systems, it is important that the algorithm designer understands their learning behavior and performance capabilities. Some simplified neural net models are analyzed in support of the simulation results. The analysis provides some theoretical basis for the usefulness of NNs for modeling satellite channels and amplifiers. The analysis of the simplified adaptive models explains the simulation results qualitatively but not quantitatively. The analysis proceeds in several steps and involves several novel ideas to avoid solving the more difficult general nonlinear problem.

Digital-to-analogue conversion using pulse width modulation

Pulse width modulation (PWM) has found application in various situations where efficient delivery of high power is required. In this paper its use in the conversion of signals from digital to analogue representations is addressed, i.e. as a digital-to-analogue converter (DAC), and it is shown that there are many advantages in using PWM over conventional DAC methods and that high resolution and accuracy can be achieved. One advantage is that, provided a suitable output stage can be provided, a complete, high-power, high-resolution digital-to-analogue power converter can be constructed. Because this work was motivated by the author's interest in digital audio, such a device has come to be known as a digital (power) amplifier. The article describes PWM, particularly in its digital forms, and shows how to make it practical for use as a DAC. This involves various digital signal processing stages prior to the final modulator. Results are presented from simulations and from demonstrator hardware.