Digital Delay-locked Loop Research Articles

A digital delay locked loop with a monotonic delay line

AbstractThis paper proposes a digital delay locked loop (DLL) with a monotonic delay line (DL). This DLL adopts the calibration mode to reduce the non‐monotonic effects for the coarse‐tuning delay line (CTDL) and the fine‐tuning delay line (FTDL). The calibration mode detects the delay time of the delay unit, the timing resolution of CTDL, to adjust the delay range of the FTDL. Thus, the calibration mode can limit the overlap range of the delay time between the CTDL and the FTDL. The proposed DLL was implemented using a 0.18‐μm CMOS process, and the RMS and the peak‐to‐peak jitters of the DLL were 0.21% and 1.72%, respectively, at 560 MHz.

Impact of neutron induced Single-Event Multiple Transients in ADDLL based frequency multiplier

This paper presents the impact of radiation-induced Single-Event Multiple Transients (SEMT) in All Digital Delay-Locked Loop (ADDLL) and its impact on the output of frequency multiplier. The performance of the frequency multiplier such as the phase noise and jitter etc. are degraded due propagation of the SEMT from the ADDLL. This paper: (1) shows the impact of SEMTs in the ADDLL in modern technologies, (2) shows how the frequency multiplier circuit performance can vary depending on the severity of SEMTs effects, and (3) demonstrates proposed edge-combined ADDLL based frequency multiplier performance benefits for more reliable operation.

A 1.3–4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line

A 1.3–4-GHz quadrature-phase digital delay-locked loop (DDLL) with sequential delay control and a reconfigurable delay line is designed using a 28 nm CMOS process. The time resolution of the DDLL is reduced by updating the delay code sequentially. A bidirectional shift register enables this operation with low power, resulting in bang-bang jitter that is three times smaller than that of a conventional DDLL. Conventional delay control is replaced with sequential delay control after a DDLL lock to reduce the locking time. A DDLL with a wide operation range is achieved with a reconfigurable delay line. Unlike the conventional DDLL, the minimum delay difference is adjustable in the proposed structure. To achieve a wide frequency range, the minimum delay difference of the quadrature clock is increased or decreased in three operation modes. To compensate for local variations in the CMOS process, a skew calibration circuit is implemented with the DDLL. The hardware cost of skew calibration is minimized with the proposed DDLL because it shares the subblocks for sequential delay control. The average phase difference from the quadrature clocks becomes the reference for the 90° phase for skew correction. A duty-cycle corrector (DCC) is implemented by collecting the positive edges of the quadrature-phase clocks. The DDLL consumes 6.5 mW at the maximum clock frequency of 4 GHz. The peak-to-peak jitter is improved from 15.6 to 12.5 ps with sequential delay control.

20-ps Resolution Clock Distribution Network for a Fast-Timing Single-Photon Detector

The time resolution of active pixel sensors whose timestamp mechanism is based on time-to-digital converters is critically linked to the accuracy in the distribution of the master clock signal that latches the timestamp values across the detector. The clock distribution network (CDN) that delivers the master clock signal must compensate process-voltage-temperature variations to reduce static time errors (skew) and minimize the power supply bounce to prevent dynamic time errors (jitter). To achieve sub-100-ps time resolution within pixel detectors and thus enable a step forward in multiple imaging applications, the network latencies must be adjusted in steps well below that value. Power consumption must be kept as low as possible. In this work, a self-regulated CDN that fulfills these requirements is presented for the FastICpix single-photon detector aiming at a 65-nm process. A 40-MHz master clock is distributed to 64×64 pixels over an area of 2.4×2.4 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> using digital delay-locked loops, achieving clock leaf skew below 20 ps with a power consumption of 26 mW. Guidelines are provided to adapt the system to arbitrary chip area and pixel pitch values, yielding a versatile design with very fine time resolution.

A 7-GHz Fast-Lock Two-Step Time-to-Digital Converter-Based All-Digital DLL

This paper presents a new fast-lock all-digital delay-locked loop (DLL) for next-generation memory devices such as DDR5 SDRAMs. The proposed DLL utilizes a new two-step time-to-digital converter (TDC)-based phase detecting and tracking scheme that results in a fast lock time of less than seven clock cycles. Unlike previous TDC-based DLLs, there is an advantage of having a fast lock time regardless of the long-replica clock buffer delay in the DRAM DLL. Implemented in a 65 nm CMOS process, the proposed digital DLL has a wide operating frequency range of 1.65–7.0 GHz and occupies an area of only 0.021 mm2. The DLL dissipates only 7.1 mW from a 1.0 V supply at 7 GHz, and the effective peak-to-peak (p–p) jitter of the output clock is about 4.55 ps at 7 GHz.

A Sub-100 $\mu$ m-Range-Resolution Time-of-Flight Range Image Sensor With Three-Tap Lock-In Pixels, Non-Overlapping Gate Clock, and Reference Plane Sampling

This paper aims to propose a time-of-flight (TOF) range imager with high range resolution in the sub-100 $\mu \text{m}$ range. The range imager employs a TOF measurement technique that uses an impulse photocurrent response and a three-tap lock-in pixel based on the lateral electric field modulation. To reduce the clock skew of the gating clocks, a column-parallel digital delay-locked loop (DLL) with a dual clock tree is implemented with a short calibration time of approximately 42 $\mu \text{s}$ . A non-overlapping gate clock generation included in the skew calibration circuit effectively suppresses the photogenerated-charge partitioning for reduced nonlinearity for distance measurements. Reference plane sampling (RPS) is proposed to reduce low-frequency jitter that limits the range resolution in the light-pulse trigger. In this technique, a reference pixel array is embedded in the same focal plane of the main pixel array to sample and cancel the correlated jitter in the light trigger. The prototype range imager with $192\,\,\times \,\,4$ effective pixels is implemented in a 0.11- $\mu \text{m}$ CMOS image sensor technology. Using the RPS, a range resolution of 64 $\mu \text{m}_{\mathrm {rms}}$ has been achieved, corresponding to a 430-fs time resolution with a 25-mm range. The range resolution has a large column-to-column deviation due to the jitter induced by the column-parallel gating buffers. In noisy columns, jitter that acts as random telegraph noise (RTN) is observed.

A 2.5–5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler

A low-jitter, low-power ring oscillator (RO)-based injection-locked clock multiplier (ILCM) is presented. It employs a background-calibrated reference frequency doubler to increase the RO noise suppression bandwidth, a digital delay-locked loop (DLL) to achieve second-order suppression of RO noise, and a digital frequency-tracking loop (FTL) to continuously tune the oscillator's free-running frequency and ensure a robust operation across process, voltage, and temperature (PVT) variations. A least-mean-square (LMS) algorithm is used to accurately cancel the deterministic jitter (DJ) caused by input duty cycle errors. Fabricated in the 65-nm CMOS process, the prototype ILCM occupies an active area of 0.09 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and generates an output clock in the range of 2.5-5.75 GHz using a 125-MHz reference clock. At 5 GHz, it achieves an integrated jitter of 335 fsrms, while consuming 5.3 mW of power. This translates to the best reported figure-of-merit (FoM) of -242.4 dB for a ring-based ILCM at this high frequency.

An anti-boundary switching fine-resolution digital delay-locked loop

This paper presents a new anti-boundary switching fine-resolution digital delay-locked loop (DLL) for high speed memory systems. The proposed digital DLL uses a new phase-interpolator (PI)-based digitally controlled delay line structure with overlapping period to eliminate the boundary switching problem in conventional digital DLLs, achieving high delay resolution and low jitter characteristics. In addition, by applying the phase inversion scheme and the variable successive approximation register algorithm, the proposed digital DLL achieves a fast locking time of less than 114 cycles and has a wide operating frequency range of 125 MHz–2.7 GHz without producing any harmonic lock problem. Fabricated in a 0.13-µm CMOS process, the proposed digital DLL achieves a fine delay resolution of around 2.0 ps and the measured peak-to-peak output clock jitter is only 8.75 ps at 2.7 GHz. The proposed digital DLL occupies an active area of only 0.05 mm2 and dissipates 8.6 mW of power from a 1.2 V supply at 2.0 GHz.

A Digital DLL with 4-Cycle Lock Time and 1/4 NAND-Delay Accuracy

This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NAND-delay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in a 65 ㎚ CMOS process, the proposed DLL occupies 0.0432 ㎟, and consumes 3.7 ㎽ from a 1.2-V supply at 2 ㎓.

A High-Resolution Dual-Loop Digital DLL

A new dual-loop digital delay-locked loop (DLL) using a hybrid (binary + sequential) search algorithm is presented to achieve both wide-range operation and high delay resolution. A new phase-interpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a 0.18-㎛ CMOS process, occupies an active area of 0.19 ㎟ and operates over a wide frequency range of 0.15–1.5 ㎓. The DLL dissipates a power of 11.3 ㎽ from a 1.8 V supply at 1 ㎓. The measured peak-to-peak output clock jitter is 24 ㎰ (effective pk-pk jitter = 16.5 ㎰) with an input clock jitter of 7.5 ㎰ at 1.5 ㎓. The delay resolution is only 2.2 ㎰.

DLL‐based signal conditioning system for SAW sensor with digital output

The use of a delay-locked loop (DLL) for conditioning signals from a surface acoustic wave (SAW) sensor is proposed. The system consists of a reference oscillator and a DLL. The signal generated in the reference oscillator is propagated through a sensitive SAW delay line (SAW-DL). The SAW propagating through this structure has a phase velocity dependent on environmental parameters such as temperature, humidity, mechanical deformation, or analyte concentration. Therefore, the system measures the physical quantity of interest by tracking the delay caused by the sensitive SAW-DL via a DLL. Fully digital DLL is made use of for the delay-tracking, which provides the conversion of the environmental parameter being sensed directly to the digital domain. The system is demonstrated through results from behavioural simulation, using a model of an SAW-DL sensitive to humidity.

A Fast-Locking Digital Delay-Locked Loop with Multiphase Outputs using Mixed-Mode-Controlled Delay Line

This paper proposes a fast-locking digital delay-locked loop (DLL) with multiphase outputs using mixed-mode-controlled delay line (MCDL). The proposed DLL uses a dual-loop technique to control various MOS capacitors and an MOS resistor in the MCDL to improve locking time and reduce static phase error. The chip was fabricated using a 0.35 µm standard CMOS process with a 3.3 V supply voltage. The measurement results showed that the proposed DLL can operate correctly with the input clock frequency varying from 145 MHz to 245 MHz. After the DLL is locked, it can generate four-phase clocks within a single clock cycle. At 180 MHz, the measured root-mean-square jitter and peak-to-peak jitter were 10 ps and 70 ps, respectively. The total power consumption of the DLL was 15 mW, and the active area of the DLL was 0.086 mm 2 . The locking time was less than 30 clock cycles.

A High Efficiency Active Rectifier for 6.78MHz Wireless Power Transfer Receiver with Bootstrapping Technique and All Digital Delay-Locked Loop

This paper presents a new rectifier with a bootstrapping technique to reduce the effective drop voltage. An all-digital delay locked loop (ADDLL) circuit was also applied to prevent the reverse leakage current. The proposed rectifier uses NMOS diode connected instead of PMOS to reduce the design size and improve the frequency respond. All the sub-circuits of ADDLL were designed with low power consumption to reduce the total power of the rectifier. The rectifier was implemented in CMOS 0.35 μm technology. The peak power conversion efficiency was 76 % at an input frequency of 6.78MHz and a power level of 5W.

An 8 Gb/s–64 Mb/s, 2.3–4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS

A burst-mode transmitter achieves 6 ns turn-on time by utilizing a fast frequency settling ring oscillator in digital multiplying delay-locked loop and a rapid on-off biasing scheme for current mode output driver. The resistor tuning-based ring oscillator avoids the use of bias voltages and thereby eliminates the related settling time overhead. The calibrated rapid on-off biasing circuit utilizes a fast charging technique to achieve bias voltage settling time of 4 ns, resulting in 30X improvement over a diode-connected bias circuit. Fabricated in 90 nm CMOS process, the prototype achieves 2.29 mW/Gb/s energy efficiency at peak data rate of 8 Gb/s. A 125X (8 Gb/s to 64 Mb/s) change in effective data rate results in 67X (18.29 mW to 0.27 mW) change in transmitter power consumption corresponding to only 2X (2.29 mW/Gb/s to 4.24 mW/Gb/s) degradation in energy efficiency for 32 byte long data bursts. We also present an analytical bit error rate (BER) computation technique for rapid on-off links, which uses MDLL settling measurement data in conjunction with always-on transmitter measurements. This technique indicates that the BER bathtub width for 10 -12 BER is 0.65 UI and 0.72 UI during rapid on-off operation and always-on operation, respectively.

An Implementation of Wide-Range Digital Delay Locked Loop

This paper presents an all digital delay-locked loop (DLL) to achieve wide range operation, fast lock and process immunity. To keep track of any potential phase problem caused by environmental variations, a delay compensation mechanism is employed. Utilizing the delay compensation controller (DCC), the proposed DLL can overcome the false-lock problem in conventional designs. It is fast locking because the DLL’s initial state can be detected by the delay compensation controller and the initial large phase difference can be eliminated. The proposed DLL is implemented in a 0.13μm CMOS process. The experimental result shows that the chip could work in a wide frequency range from 10 MHz to 1 GHz, with less than 20 cycles lock-in time, 10-ps delay resolution, and 6.4 mW at 1 GHz power dissipation.

An Improved SAR Controller for ADDLL Used in DVFS System

An improved successive approximation register (SAR) controller for all digital delay-locked loops (ADDLLs) is proposed to overcome the dead lock problem of the conventional SAR controller by embedding a restarting circuit module into the conventional SAR controller. The ADDLL that adopts the new SAR controller can track the operating frequency variation after the first lock-in, keep the advantages of the SAR searching algorithm and satisfy the requirements of DVFS systems.

Radiation-hardened-by-design clocking circuits in 0.13-μm CMOS technology

We present a single-event-hardened phase-locked loop for frequency generation applications and a digital delay-locked loop for DDR2 memory interface applications. The PLL covers a 12.5 MHz to 500 MHz frequency range with an RMS Jitter (RJ) of 4.70-pS. The DLL operates at 267 MHz and has a phase resolution of 60-pS. Designed in 0.13-μm CMOS technology, the PLL and the DLL are hardened against SEE for charge injection of 250 fC. The PLL and the DLL consume 17 mW and 22 mW of power under a 1.5 V power supply, respectively.

High-Voltage Tolerant Digitally Aided DCM/PWM Multiphase DC-DC Boost Converter With Integrated Schottky Diodes in 0.13 µm 1.2 V Digital CMOS Process

This paper reports a high-frequency DC-DC boost converter capable of sustaining up to 4× the rated process voltage using high-voltage devices fabricated in standard 0.13 μm 1.2 V CMOS without additional masking steps. Integrated Schottky Barrier Diodes (SBD) and high-voltage stacked composite NMOS switches enable processing of large voltages in a 100 MHz digitally assisted four-phase switched inductor (SI) boost converter architecture. A high-frequency digital delay-locked loop (DDLL) is employed to automatically stagger and synchronize each phase to a primary current-mode pulsed-width modulator (PWM) controller, thus eliminating the need for multiple current sensing circuits. The converter operates in discontinuous conduction mode (DCM) and utilizes integrated Schottky diode output rectifier stages to eliminate dead-time controllers and power hungry high side drivers. The converter operates at 100 MHz with four external 22 nH inductors and achieves an output conversion range of 3 V to 5 V from a 1.2 V input supply. It can deliver 240 mW at 3 V and 200 mW at 5 V with an efficiency of 60%, and ~ 180 mW at 3 V with peak efficiency of 64%.

A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces

The digital delay-locked loop (DLL) with racing mode and the countered column address strobe (CAS) latency controller are proposed in this paper. The dual-DLL architecture with racing operation is adopted to achieve low power consumption, low jitter, fast locking, wide range of locking, and stuck-free control. The merged dual coarse delay line (MDCDL) reduces the dynamic power consumption of a variable delay line by 30% by sharing a part of the delay line path in DLL. In addition, jitter is reduced by 45 ps in the 1066-DDR3 operating mode by MDCDL. The proposed DLL utilizes an or-and functioned duty cycle corrector (or-and DCC), which consumes 15% of DLL's power, 0.915 pJ/Hz at <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm tCK}=\ {\hbox {1.5 ns}}$</tex></formula> and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">${\rm VDD}=\hbox{1.575\ V}$</tex></formula> . The countered CAS latency controller (CCLC) saves IDD3N current because it does not need a DLL clock and does not need to be activated for IDD3N (active non-power down) state. The DLL clock is enabled and CCLC is activated only when the read command is issued. This operation condition saves the IDD3N current by 60% with the proposed DLL. The proposed DLL is employed in 128 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$~$</tex></formula> M <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\times$</tex></formula> 8 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$~$</tex></formula> DDR3 SDRAM and 64 M <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\times$</tex></formula> 16 DDR3 SDRAM. The former and the latter are fabricated by 5 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\times$</tex> </formula> nm and by 4 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\times$</tex> </formula> nm DRAM process technology, respectively. Experimental results show that <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\pm$</tex></formula> 10% duty error of the external clock can be corrected to within <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\pm$</tex></formula> 2% duty error in less than 512 cycles of locking time under 1.5 ns of tCK. The proposed DLL and CCLC can operate above 1.0-GHz operating frequency at 1.2 V in 5 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\times$</tex></formula> nm DDR3 SDRAM and at 1.0 V in 4 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\times$</tex></formula> nm DDR3 SDRAM, respectively. The proposed DLL fabricated with 4 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\times$</tex></formula> nm technology consumes 6.1 pJ/Hz at 1.575 V.

A 15 MHz to 600 MHz, 20 mW, 0.38 mm$^{2}$ Split-Control, Fast Coarse Locking Digital DLL in 0.13 $\mu$m CMOS

A digital delay-locked loop (DLL) suitable for generation of multiphase clocks in applications such as time-interleaved and pipelined analog-to-digital converters (ADCs) locks in a very wide (40×) frequency range. The DLL provides 12 uniformly delayed phases, free of false harmonic locking. A two-stage digital split-control loop is implemented: a fast-locking coarse acquisition is achieved in four cycles using binary search; a fine linear loop achieves low jitter (9 ps rms @ 600 MHz) and tracks process, voltage, and temperature (PVT) variations. The false harmonic locking detector, the frequency range and the jitter performance among other design considerations are analyzed in detail. The DLL consumes 20 mW and occupies a 470 μm × 800 μm in 0.13 μm CMOS.