A High-Resolution Dual-Loop Digital DLL

Abstract

A new dual-loop digital delay-locked loop (DLL) using a hybrid (binary + sequential) search algorithm is presented to achieve both wide-range operation and high delay resolution. A new phase-interpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a 0.18-㎛ CMOS process, occupies an active area of 0.19 ㎟ and operates over a wide frequency range of 0.15–1.5 ㎓. The DLL dissipates a power of 11.3 ㎽ from a 1.8 V supply at 1 ㎓. The measured peak-to-peak output clock jitter is 24 ㎰ (effective pk-pk jitter = 16.5 ㎰) with an input clock jitter of 7.5 ㎰ at 1.5 ㎓. The delay resolution is only 2.2 ㎰.