Radiation-hardened-by-design clocking circuits in 0.13-μm CMOS technology

Abstract

We present a single-event-hardened phase-locked loop for frequency generation applications and a digital delay-locked loop for DDR2 memory interface applications. The PLL covers a 12.5 MHz to 500 MHz frequency range with an RMS Jitter (RJ) of 4.70-pS. The DLL operates at 267 MHz and has a phase resolution of 60-pS. Designed in 0.13-μm CMOS technology, the PLL and the DLL are hardened against SEE for charge injection of 250 fC. The PLL and the DLL consume 17 mW and 22 mW of power under a 1.5 V power supply, respectively.