All-digital clock and data recovery circuit for USB applications in 65 nm CMOS technology

Abstract

An all-digital clock and data recovery (CDR) circuit is proposed in this work. The modified structure of multi-level bang-bang phase detector (BBPD) is proposed to eliminate the metastability problem at locking time and the phase difference of ±180°. For fine tuning of the phase, the Vernier time to digital converter (TDC) with multi-mode delay cell is proposed in order to provide various delays in the delay lines for achieving various resolutions under different conditions. For reducing the power consumption and chip area, all of the blocks designed for the CDR have digital structures. Also the scalability and tolerance to process, voltage and temperature (PVT) variations are improved in the proposed CDR with digital topology. The CDR occupies 0.02 mm2 in TSMC 65 nm CMOS technology. The total power consumption of the CDR is 2.815mW @ 10Gbit/s from 1 V power supply. The proposed CDR is designed for USB2, USB3 and USB3.1 applications and its RMS jitter can follow USB standards.