操作在1.2V電壓使用延伸線性控制範圍VCO的2.5Gbps時脈資料回復電路

Abstract

Clock and data recovery (CDR) circuit is a key component used in Ethernet, optical network and serial link. High-speed and low-power CDR circuits find their applications in a variety of communication systems. The thesis introduces the architectures and some design issues of clock and data recovery circuits. A low voltage and high speed CDR is then designed and implemented. Behavior model built by using Matlab Simulink is used to simulate and analyze the function and stability of the CDR. A 1.2V 2.5Gbps CDR circuit has been implemented in TSMC 0.18um 1P6M CMOS process. A half-rate CDR circuit using 1.25GHz VCO is presented. The VCO uses a modified delay cell to extend the linear control range to 0~1.2V for low voltage operation. The linearity and gain of the VCO transfer characteristics are much improved. The modified VCO works at a tuning range from 0.76 GHz to 1.5GHz, and its peak-to-peak jitter at 1.25 GHz is 30ps. The phase noise is -100.7dBc /Hz at 1MHz offset from a 1.25GHz center frequency. The power consumption of the core circuit is 1.8mW, with buffer is 3.21mW. The clock and data recovery circuit consumed 49.5mW at 1.2V power supply, and its jitter is 175ps. The power consumption of the half-rate phase detector is 12.7 mW. The circuit buffers consumed 33mW. For testing purpose a 2.5GHz PLL and a 215-1 PRBS generator are included in the chip. The whole chip area is 920um*920um. The CDR circuit area is 322.4um*403.3um.