Abstract
The time resolution of active pixel sensors whose timestamp mechanism is based on time-to-digital converters is critically linked to the accuracy in the distribution of the master clock signal that latches the timestamp values across the detector. The clock distribution network (CDN) that delivers the master clock signal must compensate process-voltage-temperature variations to reduce static time errors (skew) and minimize the power supply bounce to prevent dynamic time errors (jitter). To achieve sub-100-ps time resolution within pixel detectors and thus enable a step forward in multiple imaging applications, the network latencies must be adjusted in steps well below that value. Power consumption must be kept as low as possible. In this work, a self-regulated CDN that fulfills these requirements is presented for the FastICpix single-photon detector aiming at a 65-nm process. A 40-MHz master clock is distributed to 64×64 pixels over an area of 2.4×2.4 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> using digital delay-locked loops, achieving clock leaf skew below 20 ps with a power consumption of 26 mW. Guidelines are provided to adapt the system to arbitrary chip area and pixel pitch values, yielding a versatile design with very fine time resolution.
Highlights
A CTIVE pixel detectors with very fine time resolution are an attractive alternative in a wide range of fast-timing imaging systems, such as medical diagnosis with positron emission tomography (PET), molecular studies with mass spectrometry imaging (MSI), and particle tracking in highenergy physics (HEP)
This ATTRACT phase-I-funded project consists of a reconfigurable singlephoton pixel detector that can be tailored in an area to different applications by means of adaptable pixel pitch and front-end signal summation, while providing a very fine single-photon time resolution (SPTR)
This result takes into account the nonidealities in the implementation of the digital DLLs (dDLLs) (ADB layout imbalances, load effects in the interface phase detector (PD)-digitally controlled delay line (DCDL), etc.) and the divergence in the fine control bit values along the line. 3 ps is the largest standard deviation for which the time error target defined in (3) is met in all corners: the peak of the INL absolute value is at most 11 ps, which leaves a room of 9 ps for jitter and other nonidealities
Summary
A CTIVE pixel detectors with very fine time resolution are an attractive alternative in a wide range of fast-timing imaging systems, such as medical diagnosis with positron emission tomography (PET), molecular studies with mass spectrometry imaging (MSI), and particle tracking in highenergy physics (HEP). With the goal of an accurate clock distribution, which is indispensable for a reliable timestamp, the CDN must include mechanisms to self-regulate the latencies, so as to reduce the impact of skew and jitter. In this work, such a CDN is proposed for the FastICpix chip [7], [8]. This ATTRACT phase-I-funded project consists of a reconfigurable singlephoton pixel detector that can be tailored in an area to different applications by means of adaptable pixel pitch and front-end signal summation, while providing a very fine single-photon time resolution (SPTR).
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