Combinational Digital Circuits Research Articles

Design and Implementation of 1-bit Full Subtractor Using FinFET

Abstract: A full subtractor is a digital combinational circuit that performs subtraction involving three bits, namely A (minuend), B (subtrahend), and Bin (borrow-in) . It accepts three inputs: A (minuend), B (subtrahend) and a Bin (borrow bit) and it produces two outputs: D (difference) and Bout (borrow out). Unlike a half adder, which adds only two binary digits and produces a sum and carry, a full adder considers an additional carry input from a previous less significant bit addition. The full adder's design includes three inputs: A, B, and Cin (carry-in), and two outputs: Sum (sum) and Cout (carry-out). The sum output Sum is derived by XOR-ing the three inputs, while the carry-out Cout is obtained by considering the majority function of the inputs. This means Cout is set when any two or more of the three inputs are high (logical 1). Full subtractors are fundamental components in the construction of arithmetic logic units (ALUs), binary adders, and other computational circuits in digital systems, enabling the handling of multi-bit binary addition by cascading multiple full adders.

A Simple Stuck-at-faults Detection Method in Digital Combinational Circuits. II

This article proposes the improved method for detecting (diagnosing) stuck-at-faults (0/1) in PIPO-type digital combinational circuits described by a system of logical functions. Compared to already known methods and algorithms, the presented approach is characterized by a simpler implementation of the search for vectors of the test codes for detection of such malfunctions at arbitrary points of a logic circuit with many outputs due to the usage of several simple numerical set-theoretic operations and procedures. The given examples prove the advantages of the proposed method.

Evolving Multi-Output Digital Circuits Using Multi-Genome Grammatical Evolution

Grammatical Evolution is a Genetic Programming variant which evolves problems in any arbitrary language that is BNF compliant. Since its inception, Grammatical Evolution has been used to solve real-world problems in different domains such as bio-informatics, architecture design, financial modelling, music, software testing, game artificial intelligence and parallel programming. Multi-output problems deal with predicting numerous output variables simultaneously, a notoriously difficult problem. We present a Multi-Genome Grammatical Evolution better suited for tackling multi-output problems, specifically digital circuits. The Multi-Genome consists of multiple genomes, each evolving a solution to a single unique output variable. Each genome is mapped to create its executable object. The mapping mechanism, genetic, selection, and replacement operators have been adapted to make them well-suited for the Multi-Genome representation and the implementation of a new wrapping operator. Additionally, custom grammar syntax rules and a cyclic dependency-checking algorithm have been presented to facilitate the evolution of inter-output dependencies which may exist in multi-output problems. Multi-Genome Grammatical Evolution is tested on combinational digital circuit benchmark problems. Results show Multi-Genome Grammatical Evolution performs significantly better than standard Grammatical Evolution on these benchmark problems.

МЕТОД МІНІМІЗАЦІЇ БУЛЕВИХ ФУНКЦІЙ ДЛЯ ПРОЄКТУВАННЯ ЦИФРОВИХ КОМБІНАЦІЙНИХ СХЕМ

The article discusses a two-stage method of minimizing Boolean functions for designing digital combinational circuits. At the first stage, the search for simple conjuncterms is carried out by the method of bitwise division of the set of initial conjuncterms. At this way tautology does not appear, low-rank conjuncterms are found without intermediate gluing. At the second stage, the search for the minimal set of simple conjuncterms is performed by the method of chain coverage of the table of simple conjuncterms. In the cyclic part, fragments of chain functions are found, the coverage of which is quite simple. To reduce the computational load at branching points of chains, a decision can be made about entering or removing the corresponding simple conjuncterm from the finite set based on the calculation of the complexity factor in the vicinity of the branching. The proposed method is heuristic.

A Simple Stuck-at-faults Detection Method in Digital Combinational Circuits

This paper considers the new method of detection (diagnostic) stuck-at-faults (0/1) in digital combinational circuits based on a numerical set-theoretical approach. Compared to known methods and algorithms, the proposed approach differs in simpler implementation of searching for vectors of test codes at arbitrary points of the studied logic circuit. A few simple set-theoretical operations and procedures are sufficient to determine the location and the type of a stuck-at-fault (0/1). This is evidenced by the presented examples of application of the proposed method, that are borrowed from the publications of well-known authors.

Performance analysis of Ternary Adder and Ternary Multiplier without using Encoders and Decoders

This work presents comparison of ternary combinational digital circuits that reduce energy consumption in low-power VLSI (Very Large Scale Integration) design. CNTFET and GNRFET-based ternary half adder (THA) and multiplier (TMUL) circuits has been designed using ternary unary operator circuits at 32nm technology node and implement two power supplies Vdd and Vdd/2 without using any ternary decoders, basic logic gates, or encoders to minimize the number of used transistors and improve the energy efficiency. The effect of CNTFET and GNRFET parametric variation with threshold voltage on performance metrics namely delay and power has been analyzed. Dependence of threshold voltage on the geometry of carbon nanotube and graphene nanoribbon makes it feasible to be used for ternary logic design. It is analyzed that CNTFET based circuits are energy efficient than the GNRFET- based circuits. It is also concluded that the CNTFET-based circuitshas less power-delay product (PDP) when compared to GNRFET- based circuits. CNTFET-based THA is 23.5% more efficient than GNRFET-based THA and CNTFET-based Tmul is97.8% more efficient than GNRFET-based Tmul.All the digital circuits have been simulated using HSPICE tool.

An effective GDI (Gate Diffusion Input) Based 16- bit Shift Register Design for Power and Area Optimization

Abstract: Sequential circuit design is heavily influenced by power consumption and area reduction. Mainly consisted is shown here. Rather than using flip flops, pulsed latches are used to limit the amount of space these utilize. The shift register uses a minimal number of pulsed clock signals by combining the latches into numerous sub shifter registers and using Multiplexer and additional temporary storage latches. Multiple non-overlap delayed pulsed clock signal schemes are presented for data synchronization in a multi bit shift register to decrease power consumption. In order to maintain the current system, Tanner SEDIT will be used with Taiwan Semiconductor (TSMC) 0.18mm technology. Designing low-power digital combinational circuits using Gate Diffusion Input(GDI) is a common practice nowadays. When used in particular operating conditions, the GDI approach restores the in-cell swing by implementing sophisticated logic functions on two transistors. This method reduces power consumption, propagation latency, and digital circuit size while maintaining low complexity of logic design. Dual Edge Triggered Flip Flop(DETFF) implementation using GDI technology is introduced as an improvement to the shift register design. This idea also takes into account time restrictions, which can be reduced with the least amount of management. Keywords: Shift Register, Thermometer Code, Gate Diffusion Input, Dual Edge Triggered Flip-Flop, Propagation latency.

Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

Fault Detection based on Deep Learning for Digital VLSI Circuits

As growing complexity of digital VLSI circuits, fault detection and correction processes have been the most crucial phases during IC design. Many CAD tools and formal approaches have been used for debugging and localizing different kinds of design bugs. However, the search space explosion problem remains the main problem for IC designers. Recently, Artificial intelligence and machine learning models have been expanded in feature extraction and reduction models. In this paper, we introduce a new fault detection model based on deep learning for extracting features and detecting faults from large-sized digital circuits. The main goal of the proposed model is to avoid the search space using stacked sparse autoencoder, a specific type of artificial neural network. The model consists of three phases: test pattern generation using ATALANTA software, feature reduction using SSAE and classification for fault detection. Test vectors are utilized in SSAE as a training data for unsupervised learning phase. The performance of feature extraction is tested by changing the architecture of SSAE network and sparsity constraint. The proposed algorithm has been implemented using eight combinational digital circuits from ISCAS’85. From experimental results, the maximum fault coverage using ATALANTA tool delivers around 99.2% using ISCAS’85. In addition, the maximum validation accuracy of proposed SSAE model delivers around 99.7% in feature reduction phase.

Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders

Multiple-Valued Logic systems present significant improvements in terms of energy consumption over binary logic systems. This paper proposes new ternary combinational digital circuits that reduce energy consumption in low-power nano-scale embedded systems and Internet of Thing (IoT) devices to save their battery consumption. The 32 nm CNTFET-based ternary half adder (THA) and multiplier (TMUL) circuits use novel ternary unary operator circuits and implement two power supplies Vdd and Vdd/2 without using any ternary decoders, basic logic gates, or encoders to minimize the number of used transistors and improve the energy efficiency. Extensive simulations (over 160) of the proposed designs in terms of PVT (Process, Voltage, Temperature) variations, noise effect, and scalability studies, along with several benchmark designs using HSPICE simulator, prove the significance of the proposed circuits to decrease the power-delay product (PDP), improve the robustness to process variations, and the noise tolerance. The obtained results show the superiority of the designs in a reduction between 32% and 74% in transistors count and between 18% and 99% in PDP compared to the most recent works.

Design and Performance Evaluation of Energy Efficient 8-Bit ALU At Ultra Low Supply Voltages Using FinFET With 20nm Technology

ince last few years, the tiny size of MOSFET, that is less than tens of nanometers, created some operational problems such as increased gate-oxide leakage, amplified junction leakage, high sub-threshold conduction, and reduced output resistance. To overcome the above challenges, FinFET has the advantages of an increase in the operating speed, reduced power consumption, decreased static leakage current is used to realize the majority of the applications by replacing MOSFET. By considering the attractive features of the FinFET, an ALU is designed as an application. In the digital processor, the arithmetic and logical operations are executed using the Arithmetic logic unit (ALU). In this paper, power efficient 8-bit ALU is designed with Full adder (FA) and multiplexers composed of Gate diffusion input (GDI) which gained designer's choice for digital combinational circuit realization at minimum power consumption. The design is simulated using Cadence virtuoso with 20nm technology. Comparative performance analysis is carried out in contrast to the other standard circuits by taking the critical performance metrics such as delay, power, and power delay product (PDP), energy-delay product (EDP) metrics into consideration.

Development of Combinational Circuits by Encoding on the Basis of Developmental Biology.

The present work visualizes the evolution of primitive digital circuits as a development problem. The development of the digital circuit is implemented similar to the development of a human embryo from a single cell to the complete organism. The constituent parts making up a primitive digital circuit are encoded into binary strings. Each binary string is viewed as a cell, and several such cells are allowed to adhere and multiply before culminating into a developed organism. The binary string of the cell is further mapped to a particular attribute which defines the constituent of the complete digital circuit implemented. The present work illustrates the development of a 4-input combinational digital circuit. The development of 2-input majority function is illustrated, and the results are shown for the 2-input Ex-OR gate, 2-input majority function with 4 input variables, and a 2-to-1 multiplexer circuit. The development of the digital circuit resembles the development of an embryo in a living organism.

Static characteristics of CMOS digital circuit based on transition metal dichalcogenide transistors

Static characteristics of digital combinational logic circuits and Schmitt triggers based on two-dimensional (2D) transition metal dichalcogenides (TMDs) have been systematically explored. Selenide tungsten (WSe2) transistors act as the P type metal oxide semiconductor (PMOS). Molybdenum disulfide (MoS2) transistors play the role as N type metal oxide semiconductor (NMOS). Based on the circuit simulations, we find that the output of the complementary metal oxide semiconductor (CMOS) inverters and Schmitt triggers can approach the supply voltage (VDD) and ground (GND), respectively. The key performance indexes of the two digital circuits have been studied with the change of the device parameters. The simulation results indicate that a thinner gate oxide thickness and a higher dielectric permittivity gate oxide material can increase the noise margin of the inverters. Besides, different width ratios of PMOS and NMOS can influence the noise margin of inverters. An inverter with a large PMOS whose width is 64 nm and a small NMOS whose width is 32 nm can improve the low level noise margin, but reduce the high level noise margin. In addition, a gate oxide thickness of 2.8 nm can broaden the hysteresis window of the Schmitt triggers obviously. The output curves of the Schmitt triggers change slightly with different gate oxide materials. The hysteresis window of the Schmitt triggers becomes narrow with decreasing of the supply voltage. The present work could help to design the standard cells with different requirements and improve the performance of digital integrated circuits using TMDs transistors.

Reliable S-Box Hardware Implementation by Gate-Level Fault Masking Enhancement

With technology scaling, fault tolerance has become more essential for digital circuits. Some solutions, like all types of redundancies, have been proposed to increase the reliability of the systems. In this paper, we present a cost-aware algorithm to enhance the fault tolerance ability of combinational digital circuits. Proposed algorithm improves the circuit logical masking with minimum area overhead based on an improved version of genetic algorithm (GA). Given a set of potential gates that are more sensitive to fault occurrence, we first extract feasible functional redundant, ffr, between the source nodes and the potential gates’ outputs that their improvement on logical masking be more than a pre-defined threshold and hold them in a library, Masking_Lib. Then, we have to find a set of minimum number of potential gates as a target to add appropriate ffr, so that the maximum improvement on logical masking with minimum area overhead is achieved. Since, finding a set of potential gates with their suitable ffrs to meet these objectives is an NP-hard problem, we formulize this, as an optimization problem and solve using GA. We introduce an efficient chromosome representation and an adaptive objective function along with the basic GA operators. Besides, we integrate an assimilation operator with GA in order to enhance its searching ability. Our approach is applied to composite field substitution box implementation (S-box) that forms the core building block of any hardware implementation of the Advanced Encryption Standard algorithm. The simulation and synthesis results have been reported to show the effectiveness of our approach. Through these results, it has been shown that our proposed algorithm provides reliable digital circuits based on different level of logical masking (from 25.58 to 52.15).

Study and Performance Analysis of MOS Technology and Nanocomputing QCA

One of the critical issues in VLSI circuit is High Power dissipation. Quantumdot Cellular Automata (QCA) which is widely utilized in nanocomputing era. QCA has Landauer clocked based synthesis approach and it has clocked based information flow. This manuscript analysis and design a combinational digital circuits in an emerging QCA framework. The design is evaluated and formulated in terms of area, latency and power dissipation. QCA Designer tool has been taken for the design of quantum cell-based combinational circuits and simulation purpose. Moreover, it is believed based on experimental analysis that the QCA based combination circuits will make a contribution to high computing speed and low power paradigm.

Gate Diffusion Input Technique-Applications and Modifications: An Overview

This paper primarily focuses on Gate Diffusion Input (GDI) technique used for the implementation of digital logic circuits. It also discusses in detail the limitations and modifications of the basic GDI technique. Initially, GDI was a new technique used for low power digital combinational circuit design. This approach provides a reduction in power consumption, propagation delay, and area of digital circuits while the logic design complexity is small. GDI methodology allows implementation of a wide range of complex logic functions using only two transistors. GDI is a new technique for digital circuits implementation with a lot of advantages over existing ones. This paper also analyzes the recent applications of GDI technique which are the implementation of MASH 1-1 and MOD 2 modulator for Sigma Delta DACs and development of full adders for efficient arithmetic operations.

Implementation of 32-Bit Carry Select Adder using Brent-Kung Adder

The circuit used to add the two numbers or two bits is adder. The main problem with the adder is both the area and delay to produce the final output. So, this paper implements an adder it requires a less amount of delay and area to produce the final output. The reduction of delay and area is done by the Parallel Prefix Adders. It plays a prominent role in Digital Combinational Circuits. Area and power are other factors which really makes the adder effective. The techniques used to get a less amount of delay and area is by using the Binary-to-Excess-1 Converter (BEC) and a Parallel Prefix Adder. The delay of the Modified Linear Carry Select Adder of Brent Kung Adder is less when compared with the Regular Carry Select Adder architecture. The delay and area further can be improved by using a Square root Carry Select adder. This paper focuses on operation of Parallel Prefix Adders of 32 bit Brent-Kung Adder. Keywords: And-Or-Inverter (AOI) Logic, Binary-to-Excess-1 Converter (BEC), Brent-Kung (BK) Adders, Carry Select Adder (CSLA), Parallel Prefix Adder

Implementation of all-optical NAND logic gate and half-adder using the micro-ring resonator structures

The computation of digital combinational and sequential logic functionality in the optical domain is one of the most important aspects, which opens the door of fast, secure and efficient switching and communication activity in the modern technological scenario. The proposed paper describes the working optical micro-ring resonator and its application as power optical switching device. Micro-ring resonator constructed by the non-linear material (GaAs–AlGaAs) behaves as powerful optical switching devices. Now, the proper configurations and appropriate arrangement of optical micro-ring resonator gives the concepts related to the realization of the optical NAND and Half adder functionality. Hence paper describes the theoretical aspects for the implementation of all-optical NAND logic gate and one of the most important combinational digital circuits as half adder. The paper includes the relevant MATLAB simulation result, which describes the working of proposed optical logic device.

Minimization of Area and Power in Digital System Design for Digital Combinational Circuits

This paper proposes enhanced parallel adder architectures with low power and reduced area. It includes, design of three different parallel adders such as Ripple Carry Adder (RCA), Carry Look ahead Adder (CLA) and Carry Select Adder (CSA). All three adders are designed in Gate Diffusion Interface (GDI) technique as well as traditional CMOS method. Adder is a basic common combinational digital circuit. Adders are important components in signal processing, image and video processing applications. So it is essential to have compact, low power adder design for these application fields. GDI based digital system design offers reduction in power consumption and area over head. When compared to traditional CMOS based design, GDI uses very less transistor to implement a function. The GDI and CMOS methods are taken in to account for the comparison of design parameters such as design layout, node to node delay, total power dissipation and speed of operation. All three parallel adders are designed in traditional CMOS as well as GDI method. The simulations are done using Microwind2 and DSCH2 analysis software tools and the results between those two types are listed below. This proposed adder circuits can be used in all high speed multipliers and filter designs where low power and reduced area is a major concern.