Digital CMOS Process Research Articles

A Dual-Mode Step-Down Converter with Automatic Mode Switch Circuit for System-on-Chip Applications

In this paper, a dual-mode step-down DC-DC converter with an automatic mode-switching circuit is implemented in a 28 nm digital CMOS process and embedded in an RF transceiver chip to power the digital part. The proposed automatic mode-switching circuit includes a frequency-voltage conversion circuit that is designed according to the principle of charge redistribution on capacitance. The converter can switch modes according to the load without external intervention. This converter, along with a PMU sequencer, can also provide a solution for low-power design for system-on-chip applications. The IC occupies a total die area of 0.378 mm2. The input voltage of the converter is 3.3 V, the output voltage is 1.05 V, and the maximum load current can reach 1 A. The converter shows a conversion efficiency of not less than 81% at a full load range and can achieve a peak conversion efficiency of 91% when the load current is 100 mA. The load range of the PWM mode is 1 A to 50 mA, and that of the PFM mode is 100 mA to 1 mA. The combination of zero-crossing detection circuitry and freewheel switches can reduce energy loss and eliminate additional electromagnetic interference.

A Fast Lock-In Time, Capacitive FIR-Filter-Based Clock Multiplier with Input Clock Jitter Reduction

This paper presents a fast lock-in time clock frequency multiplier without using traditional clock generation circuits such as PLLs and DLLs. We propose a novel technique based on capacitive finite impulse response (FIR) filters to generate clock phases while reducing the input clock phase noise at the same time. A new delay line circuit is also proposed for improving power supply rejection. In addition, to improve the matching quality as well as the end-effects tolerance of the on-chip capacitors, a single-value series/parallel algorithm is proposed. Designed in a 0.18 μm digital CMOS process, with a 20 MHz input clock frequency, the multiplier achieves a multiplication factor of 5 with a lock-in time of less than 4 clock cycles. The input clock jitter is reduced from 7ns RMS to 153 ps RMS after frequency multiplication.

NANO-studio, the design environment of filter banks implemented in standard CMOS technology

The paper presents a method of optimizing frequency characteristics of filter banks in terms of their implementation in digital CMOS technologies in nanoscale. Usability of such filters is demonstrated by frequency-interleaved (FI) analog-to-digital converters (ADC). An analysis filter present in these converters was designed in switched-current technique. However, due to huge technological pitch of standard digital CMOS process in nanoscale, its characteristics substantially deviate from the required ones. NANO-studio environment presented in the paper allows adjustment, with transistor channel sizes as optimization parameters. The same environment is used at designing a digital synthesis filter, whereas optimization parameters are input and output conductances, gyration transconductances and capacitances of a prototype circuit. Transition between analog s and digital z domains is done by means of bilinear transformation. Assuming a lossless gyrator-capacitor (gC) multiport network as a prototype circuit, both for analysis and synthesis filter banks in FI ADC, is an implementation of the strategy to design filters with low sensitivity to parameter changes. An additional advantage is designing the synthesis filter as stable infinite impulse response (IIR) instead of commonly used finite impulse response (FIR) filters. It provides several dozen-fold saving in the number of applied multipliers.. The analysis and synthesis filters in FI ADC are implemented as filter pairs. An additional example of three-filter bank demonstrates versatility of NANO-studio software.

An Energy-Efficient 3Gb/s PAM4 Full-Duplex Transmitter With 2-Tap Feed Forward Equalizer

We present a full-duplex 3 Gb/s PAM4 voltage-mode transmitter with an embedded 2-tap feed forward equalizer. In full-duplex mode, the transmitter employs an echo canceller to cancel the locally transmitted signal and recover the signal from the far-end. The transmitter achieves energy proportionality with output swings and equalizer coefficients. Fabricated in 65 nm Digital CMOS process, the transmitter transmits a maximum of 1 V peak-to-peak differential output swing. In full-duplex mode, the transmitter equalizes 2 m UTP cable and dissipates 37.3 mW at 3Gb/s with echo canceller in the receiver path. The power reduces to 18.3 mW while transmitting across a 9 m UTP cable in the half-duplex mode.

A 1770-$\mu$ m2 Leakage-Based Digital Temperature Sensor With Supply Sensitivity Suppression in 55-nm CMOS

This article presents a leakage-based digital temperature sensor with reduced supply sensitivity for on-chip thermal management. The sensor, featured with a novel supply sensitivity suppression mechanism, performs the temperature-to-frequency conversion by a leakage-dominated ring oscillator (LDRO) with exponential temperature dependence. Thanks to the proposed robust and reconfigurable Schmitt-trigger-based delay cell, both NMOS and PMOS leakage-based sensors can be evaluated in a single design. Fabricated in a standard 55-nm CMOS digital process, the proposed digital temperature sensor occupies a silicon area of only 1770 $\mu \text{m}^{2}$ and can operate under a supply ranging from 0.8 to 1.3 V, with the supply sensitivities of 2.53–5.22 °C/V and 2.84–5.76 °C/V in two working modes at room temperature, respectively. Measurement results show that the sensor achieves an inaccuracy of ±0.70 °C (3 $\sigma $ ) from −40 °C to 125 °C after two-point calibration.

Cost-Effective 4 GHz VCO Using Only Miniature Spirals Realized in a 0.18 μm CMOS Process for Wireless Sensor Network (WSN) Applications

This paper presents an extremely cost-effective radio-frequency integrated circuit (RFIC) implementation technique by employing a digital logic CMOS process and reducing area occupation for voltage-controlled oscillators (VCOs) using all miniature inductors for wireless sensor network (WSN) applications. The designed VCO operates in the 4.0 GHz band with a power consumption of 1.4 mW and a phase noise of −113.6 dBc/Hz at 1 MHz, occupying a Si area of 0.283 × 0.682 mm2. In addition, we confirmed that the figure of merit (FOM) of 183.8 in our design is competitive with that of other LC-VCOs that were fabricated using the RF option and designed with conventional inductors.

An Untrimmed BJT-Based Temperature Sensor With Dynamic Current-Gain Compensation in 55-nm CMOS Process

This brief presents a bipolar junction transistor (BJT)-based CMOS temperature sensor without trimming. A current-mode readout scheme with dynamic current gain compensation is proposed to reduce the error caused by the low current gain $\beta $ of the substrate BJT in nanometer CMOS technologies. Combining this readout scheme with techniques, such as chopping and dynamic element matching (DEM), the sensor achieves a high untrimmed accuracy for auto-calibration in thermal management applications. Fabricated in a standard digital 55-nm CMOS process, the sensor shows a measured inaccuracy within ±1.7 °C ( $3\sigma $ ) from −40 °C to 125 °C without calibration. It occupies a die area of 0.0146 mm2 and has a power consumption of $37~\rm \mu \text{W}$ with an adjustable resolution from 12 to 15 bit and a conversion time of 4.1–32.8 ms.

A Low-Voltage Low-Phase-Noise 25-GHz Two-Tank Transformer-Feedback VCO

This paper presents a low-voltage low-phase-noise LC voltage-controlled-oscillator (VCO) with a novel two-tank transformer-feedback topology. The flicker noise up-conversion is suppressed by making the drain impedance of the cross-coupled transistors to be a real number at the second harmonic of the oscillation. The loaded quality factor is boosted and the noise contribution from the transconductor of the VCO is reduced by introducing a negative source impedance. A prototype VCO based on this topology is demonstrated in a 65 nm digital CMOS process. The VCO is operated from 23.9 to 26.9 GHz at a low supply voltage of 0.6 V, while achieving an ultra-low 1/ $f^{3}$ phase noise corner from 170 to 240 kHz across the tuning range. The phase noise is −110 dBc/Hz at 1 MHz frequency offset. The power consumption is 4.8 mW. The measurement results demonstrate that the VCO achieves a state-of-the-art phase noise performance in both the 1/ $f^{2}$ region and the 1/ $f^{3}$ region.

Integrated Angle-Insensitive Nanoplasmonic Filters for Ultraminiaturized Fluorescence Microarray in a 65 nm Digital CMOS Process

In this work, we demonstrate for the first time massively parallelizable nanoplasmonic structures and integration of electronics in the same substrate in CMOS. We adopt the same “fabless” approach in today’s semiconductor industry with absolutely “no change” of either fabrication or processing and show that copper interconnects in an industry standard digital CMOS process (65 nm node) can be exploited to allow subwavelength optical field processing in a massively scalable fashion. We demonstrate this in the context of eliminating all external optics and enabling the first optics-free fully integrated CMOS fluorescence-based biosensor array. The system has massively multiplexed biomolecular sensing capability for DNAs with surface sensitivity comparable to commercial fluorescence readers. The angle and scattering insensitive nature of the filter, relying on coupled surface-plasmon polariton modes, allows us to eliminate all external optics and miniaturize the entire 96-sensor array system (including a LED ...

An Integrated DC–DC Boost Converter Having Low-Output Ripple Suitable for Analog Applications

This paper presents an integrated boost converter having very low output voltage ripple making it suitable for analog applications, which are sensitive to supply noise. Architecturally, the converter consists of a conventional boost converter followed by an L–C filter, which drastically reduces the output ripple. The L–C filter has been realized using 30-nH bondwire inductance and 0.54-nF on-chip capacitance. The converter switches at 118 MHz and produces a regulated 3.2-V output from an input voltage ranging from 1.0 to 2.7 V. The converter is able to deliver up to 65-mA current for input voltage $\geq$ 2.4 V. The prototype has been implemented in 0.18- $\mu$ m standard digital CMOS process and the entire design consumes only 0.52-mm $^2$ chip area resulting in a maximum power density of 0.387 W/mm $^2$ . Peak efficiency of the converter is 77.4% at 32.2-mA current for 2.7-V input supply. The measured maximum output ripple noise is 21 mV that is less than 0.65% of the regulated output voltage.

A Miniature Mode Reconfigurable Inductorless IR-UWB Transmitter–Receiver for Wireless Short-Range Communication and Vital-Sign Sensing

This paper presents a miniature inductorless impulse-radio ultra-wideband transmitter–receiver and radar for wireless short-range communication and vital-sign sensing. The all-digital transmitter generates impulse-radio ultra-wideband pulses using edge combining technique and consumes 21.6 pJ/pulse at 10 Mb/s. A novel active-inductor-based technique is proposed for low noise amplifier that achieves ultra-wideband input impedance matching in the receiver. The non-coherent receiver employs a simple demodulation and synchronization circuit to achieve self-synchronization without any on-chip or external oscillator. Consuming a total power of 6.4 mW, the receiver attains −64-dBm sensitivity at 10 Mb/s. The chip is implemented in a 65-nm digital CMOS process and occupies only 0.04 mm2. Measurement shows that the transmitter–receiver and radar is capable of sensing the human’s respiratory rate when the time interval is measured by a fast sampling digital oscilloscope.

Design of Digital CMOS Neuromorphic IC with Current-starved SRAM Synapse for Unsupervised Stochastic Learning

This paper proposes a current-starved SRAM circuit for use as a synapse to support a biological learning of spike-timing dependent plasticity. If the driving strength of SRAM is limited both when writing a new state and restoring the previous state, then programming the opposite synaptic weight requires several densely-repeated write operations. The synapse takes only stochastically-meaningful stimuli for training, and rejects random and noisy inputs; as a result it achieves successful learning even with binary SRAM. The proposed synapse is applied to a three-layer neuromorphic network of spiking neurons that includes a receptive synaptic array and a projective synaptic array. The network is designed with a 28-nm digital CMOS process. Applying an unsupervised learning to only the projective synapses with the receptive synapses fixed at randomly given, the network successfully memorizes multiple overlapped image patterns and recalls the trained patterns if the images are distorted.

Decoupling Structures for Millimeter Wave Integrated Circuits in Digital CMOS Processes

This brief studies the effect of nonideal decoupling structures on the performance of single-ended circuits operating at the millimeter wave frequency range. Based on a first-order approximation, an upper limit on the impedance of decoupling structures is derived, given a prespecified accepted degradation in insertion loss. To verify the analysis, a 110-GHz single-ended amplifier with a compact decoupling structure based on distributed interdigitized metal-oxide-metal capacitor is implemented. The full-wave electromagnetic simulations of the decoupling structure show an input impedance of (0.47 – j0.12) $\Omega $ at 110 GHz, and the magnitude is less than $1~\Omega $ from 82 to 144 GHz. The degradation in the insertion loss of the matching network is simulated to be less than 0.5-dB compared with the use of ideal decoupling capacitors at 110 GHz. The area of the decoupling structure is $18\times 100 ~\mu \text{m}^{2}$ when implemented in 65-nm digital CMOS process.

A 20-nW 0.25-V Inverter-Based Asynchronous Delta–Sigma Modulator in 130-nm Digital CMOS Process

This paper presents a new inverter-based architecture that implements an asynchronous delta–sigma modulator. Different from the classical architecture, it features an input transconductor that promotes a differential and high input impedance that makes it easier to interface with sensors and other front ends. Furthermore, an inverter-based relaxation oscillator accomplishes the required hysteresis through a charge redistribution process, which exhibits lower time delay than hysteretic comparators, besides saving power from quiescent biasing. The circuit has been implemented in 130-nm CMOS digital process using halo-implanted transistors. In addition, transistors are biased in weak inversion and are implemented using distributed layout to reduce power consumption besides mitigating halo-implants undesired effects. Supplied with 0.25 V, the proposed architecture consumes 20 nW with just −55 dB of third harmonic distortion, making it suitable for wearable biomedical applications where energy consumption, low bandwidth, and moderate resolution are required.

A DAC With an Impedance Attenuator and Distortion Analysis Using Volterra Series

An impedance attenuator is implemented to reduce digital-to-analog converter (DAC) distortion, and two techniques to further reduce the distortion are discussed: the first is to use cross-coupled capacitors to cancel nonlinear currents; the second is to optimize the common-mode bandwidth of the differential amplifier for cancellation of distortion. To support these techniques, DAC distortion has been analyzed with the Volterra series, and the analysis is compared with simulation results and measurement data. The analysis uncovers a previously unknown nonlinear cancellation mechanism for the DAC and confirms the proposed techniques. Each technique can contribute 3–6 dB of improvement, and about a 6-dB improvement when combined. The 0.708-mm2 DAC is fabricated in a 28-nm metal-gate digital CMOS process with the proposed impedance attenuator, and it achieves −89 dBc of average HD3 at a 5-MHz input frequency and sampling rate of 230.4 MHz.

A mmWave Folded Substrate Integrated Waveguide in a 130-nm CMOS Process

A miniaturized millimeter-wave substrate integrated waveguide (SIW) in IBM 130-nm digital CMOS process is presented in this paper. The footprint of the interconnect is reduced compared with previous works using the folding technique. A current-loop transition structure is proposed in this paper that is built inside the SIW interconnect and excites its TE10 mode with minimal area overhead. A simulation-based comparison of T-FSIW and other planar transmission line structures reveals that the T-FSIW interconnect shows a much higher resonant quality factor. A prototype waveguide is designed and fabricated to operate with a cutoff frequency of 175 GHz. Furthermore, the current-loop excitation is optimized for the frequency range of 180–220 GHz. Simulation and experimental data are used to confirm the proposed interconnect approach.

High-Efficiency Millimeter-Wave Energy-Harvesting Systems With Milliwatt-Level Output Power

The output power level and the power conversion efficiency (PCE) rate of the energy-harvesting systems are vital factors in realizing effective millimeter-wave wireless power transfer solutions that can power battery-less and charge coil-free smart everyday objects. Two 60-GHz energy harvesters that use a tuned complementary cross-coupled oscillator-like rectifying circuitry in 40-nm digital CMOS process are presented. They harvest energy at power rates and peak PCE levels in excess of 1 mW and 30%. These figures are significantly higher than those of the prior art. In one design, two rectifier stages are in a cascode configuration to produce higher dc output voltage levels at the low-current regime. Novel theoretical analyses of the unique rectifying circuitry of the single-stage and two-stage cascode harvesters are presented, which formulate all of the key specifications.

A 0.4% PAE 194-GHz Signal Source With 1.5-mW Output Power in 65-nm Bulk CMOS Technology

This letter presents an amplifier-frequency doubler chain in thin digital 65-nm bulk CMOS process. Injection locking is applied to the amplifier to increase the power gain and compensate for the conversion loss in the frequency doubler. The doubler uses a compact low-impedance transmission line (LZ TLine) for effective dc decoupling in the output matching network. Measurement results show a peak output power of 1.5 mW at 194 GHz, and a peak PAE of 0.4% at 196 GHz. The locking range is measured as 8.5 GHz (92.5~101 GHz) with 2-dBm input fundamental power, and can be extended to 15 GHz with 4-dBm input power.

A Compact 60-GHz Wireless Power Transfer System

The first reported full-system 60-GHz wireless power transfer (WPT) solution that can power batteryless and charge coil-free compact WPT devices is presented. The system is fabricated in a 40-nm digital CMOS process and an inexpensive packaging material. In the rectenna (RX), a grid antenna is integrated with a complementary cross-coupled oscillator-like rectifier. At a 4-cm spacing from the transmitter (TX), the RX harvests energy at a rate of 1.22 mW with a 32.8% efficiency, which is significantly higher than the prior state of the art. A novel theoretical analysis of the rectifier operation is presented that formulates all key specifications. The TX is equipped with a quad-core PA that produces a saturated output power ( $P_{\mathrm{ sat}}$ ) of 24.6 dBm, which is the highest power delivery in digital CMOS at millimeter-wave bands. The TX peak power-added efficiency is 9.4%. In the TX, a $4 \,\, \times \,\, 8$ -way differential power combining and a binary-tree architecture are implemented. The designed $2 \times 2$ grid array antenna helps the TX produce 35.3-dBm peak equivalent isotropically radiated power. The results of the performance characterizations of the full-system and all individually fabricated blocks are reported. The quad-core PA supports power control and beam steering. A four-port TX antenna is designed that shows a 70° steering range in simulations.

High-Speed CMOS Frequency Dividers with Symmetric In-Phase and Quadrature Waveforms

Frequency dividers are used in frequency synthesizers to generate specific frequencies or clock (CK) waveforms. As consequences of their operating principles, frequency dividers often produce output waveforms that exhibit duty cycles other than 50%. However, some circuits and systems, including dynamic memory systems and data converters, which accommodate frequency divider outputs, may need symmetric or 50%-duty-cycle clock waveforms to optimize timing margins or to obtain sufficient timing reliability. In this review paper, design principles and methods are studied to produce symmetric waveforms for the in-phase (I) and quadrature (Q) outputs of high-speed CMOS frequency dividers with design considerations from the logic gate level down to the transistor level in terms of speed, reliability, noise, and latency. A compact and robust multi-gigahertz frequency divider with moduli 12, 14, and 16 to provide I and Q outputs with 50% duty cycle is proposed and designed using a 90-nm digital CMOS process technology with 1.2-V supply.