Digital CMOS Process Research Articles

Micromachined high-Q inductors in a 0.18-μm copper interconnect low-k dielectric CMOS process

On-chip spiral micromachined inductors fabricated in a 0.18-/spl mu/m digital CMOS process with 6-level copper interconnect and low-K dielectric are described. A post-CMOS maskless micromachining process compatible with the CMOS materials and design rules has been developed to create inductors suspended above the substrate with the inter-turn dielectric removed. Such inductors have higher quality factors as substrate losses are eliminated by silicon removal and increased self-resonant frequency due to reduction of inter-turn and substrate parasitic capacitances. Quality factors up to 12 were obtained for a 3.2-nH micromachined inductor at 7.5 GHz. Improvements of up to 180% in maximum quality factor, along with 40%-70% increase in self-resonant frequency were seen over conventional inductors. The effects of micromachining on inductor performance was modeled using a physics-based model with predictive capability. The model was verified by measurements at various stages of the post-CMOS processing. Micromachined inductor quality factor is limited by series resistance up to a predicted metal thickness of between 6-10 /spl mu/m.

A "digital" 6-bit ADC in 0.25-μm CMOS

Traditionally, circuit designers have adopted analog techniques to overcome comparator offset in flash converters. These schemes have an adverse effect on area and power consumption and, more seriously, do not scale easily to low-voltage processes. We describe a digital technique which removes the accuracy constraints from the comparators. With no analog matching requirements, the comparators can be small, fast, and power efficient. A 6-bit prototype converter built in a standard 0.25-/spl mu/m digital CMOS process occupies 1.2 mm/sup 2/ and dissipates 150 mW from a 2.2-V supply at 400 MS/s.

A mixed‐mode polynomial‐type CNN for analysing brain electrical activity in epilepsy

AbstractIn this paper, a mixed‐mode polynomial‐type cellular neural network (CNN) for analysing brain electrical activity in epilepsy is presented. The principles and design characteristics of this application are overviewed. The main difference of the requirements of this application compared to conventional CNN realizations is that in addition to linear, cells are also coupled with polynomial‐type couplings. A mixed‐mode CNN is shown to be suitable for the realization of a polynomial‐type CNN in the brain electrical activity analysis application. In a mixed‐mode CNN multiplication is done in analog domain, whereas the integration and storage are digital. Suitability of different integration methods for cell level realization are studied and cell and network level design of a mixed‐mode CNN is described. First‐, second‐ and third‐order polynomial feedback terms are included in the cell and Heun's integration method is used. In order to reduce the cell count, the array is designed so that it can process input data that has been divided into blocks. The whole input data is stored in parallel with the cells so that all input/output operations during processing are local. Cell structure is shown along with register connections between edge cells of the network. Analog power consumption and computing speed are estimated by HSPICE simulations using 0.25 µm digital CMOS process parameters. The die area of a network with 2×72 cells with 36 layers in each was determined by drawing the layout. Copyright © 2002 John Wiley & Sons, Ltd.

Measurements and analysis of PLL jitter caused by digital switching noise

When integrating analog and digital circuits onto a mixed-mode chip, power supply noise coupling is a major limitation on the performance of the analog circuitry. Several techniques exist for reducing the noise coupling, of which one of the cheapest is separating the power supply distribution networks for the analog and digital circuits. Noise coupling from a digital noise-generating circuit through the power supply/substrate into an analog phase-locked loop (PLL) is analyzed for three different power supply schemes. The main mechanisms for noise coupling are identified by comparing different PLLs and varying their bandwidths. It is found that the main cause of jitter strongly depends on the power supply configuration of the PLL. Measurements were done on mixed-mode designs in a standard 0.25-/spl mu/m digital CMOS process with a low-resistivity substrate. The same circuits were also implemented with triple-well processing for comparisons.

A 1.8-V MOSFET-only ΣΔ modulator using substrate biased depletion-mode MOS capacitors in series compensation

A low-voltage high-linearity MOSFET-only /spl Sigma//spl Delta/ modulator for speech band applications is presented. The modulator uses substrate biased MOSFETs in the depletion region as capacitors, linearized by a series compensation technique. A second-order fully differential single-loop architecture has been realized in a conventional 0.25-/spl mu/m digital n-well CMOS process without extra layers for capacitors. An SNDR of 72 dB and an SNR of 77 dB is obtained with 8-kHz signal bandwidth at an oversampling ratio of 64. The circuit consumes about 1 mW from a single 1.8-V power supply and occupies a core area of 0.08 mm/sup 2/.

A mixed-signal sensor interface microinstrument

A single-chip implementation of a microinstrumentation system is presented. The chip incorporates voltage, current, and capacitive sensor interfaces; a temperature sensor; a 10-channel, 12-bit analog-to-digital converter; and an 8-bit microcontroller with a 16-bit hardware multiplier and a 40-bit accumulator. Serial and parallel interfaces allow digital communication with a host system. Fabricated in a standard 0.35 μm digital CMOS process, the die occupies 3.8 mm×4.1 mm, operates from a nominal supply voltage of 3 V, and draws 16 mA when fully powered (850 μA standby current). To facilitate testing of the prototype, extra pads are bonded out to package pins. The chips are packaged in 132-pin ceramic pin-grid-array packages.

An ultralow-power UHF transceiver integrated in a standard digital CMOS process: architecture and receiver

A broad range of high-volume consumer applications require low-power battery-operated wireless microsystems and sensors. These systems should conciliate a sufficient battery lifetime with reduced dimensions, low cost, and versatility. Their design highlights the tradeoff between performance, lifetime, cost, and power consumption. Also, special circuit and design techniques are needed to comply with the reduced supply voltage (down to 1 V, for single battery cell operation). These considerations are illustrated by the design of a prototype receiver chip realized in a standard 0.5-/spl mu/m digital CMOS process with 0.6-V threshold voltage. The chip is dedicated to a distributed sensors network and is based on a direct-conversion architecture. The circuit operates at 1-V power supply in the 434-MHz European ISM band and consumes only 1 mW in receive mode. It achieves a -95 dBm sensitivity for a data rate of 24 kb/s.

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator

This paper describes a low-voltage low-jitter clock synthesizer and a temperature-compensated tunable oscillator. Both of these circuits employ a self-correcting delay-locked loop (DLL) which solves the problem of false locking associated with conventional DLLs. This DLL does not require the delay control voltage to be set on power-up; it can recover from missing reference clock pulses and, because the delay range is not restricted, it can accommodate a variable reference clock frequency. The DLL provides multiple clock phases that are combined to produce the desired output frequency for the synthesizer, and provides temperature-compensated biasing for the tunable oscillator. With a 2-V supply the measured rms jitter for the 1-GHz synthesizer output was 3.2 ps. With a 3.3-V supply, rms jitter of 3.1 ps was measured for a 1.6-GHz output. The tunable oscillator has a 1.8% frequency variation over an ambient temperature range from 0/spl deg/C to 85/spl deg/C. The circuits were fabricated on a generic 0.5-/spl mu/m digital CMOS process.

An ultralow-power UHF transceiver integrated in a standard digital CMOS process: transmitter

In the first part of the paper, also in this issue of the JOURNAL, the design of the frequency synthesizer and receiver section of an FSK transceiver was described. It operates in the 434-MHz ISM (Industrial, Scientific, Medical) band and is realized in a standard digital 0.5-/spl mu/m CMOS process. This companion paper focuses on the realization of the transmitter section. It includes a power amplifier, an upconverter, and the circuit generating the baseband quadrature signals with a continuous phase modulation. The overall measured efficiency of the packaged circuit is higher than 38% for a 1.2-V supply and an output power reaching 10 dBm at 433 MHz. The system is designed to still operate at 1-V supply, delivering more than 1 mW with an efficiency higher than 15%.

A new cell output nonlinearity for dense cellular nonlinear network integration

A new approach for designing a cellular nonlinear network (CNN) cell is introduced. The method can be used when the processed images are bipolar, i.e., black and white. A simple circuit realization is introduced that can be applied when building up the analog part of the cell. The cell output nonlinearity is an easily realizable positive range high gain sigmoid. Moreover, a state limited model is adopted to decrease the complexity of the design. The coefficient building blocks are simple, and also because these blocks introduce an almost error free multiplication by zero, the corresponding devices can be made relatively small due to relaxed coefficient accuracy requirements. This approach yields a very small cell area on silicon and can be used with inexpensive digital CMOS processes. Simulation results are given for both static and dynamic behavior of the proposed structure. The dynamic simulation shows very fast convergence time compared to other reported approaches for CNN very large scale integration implementation.

Analysis of manufacturability factors for analog CMOS ADC building blocks

In this paper, the layout of analog CMOS integrated circuits is considered as one of the most important manufacturability factors. Various layout design styles are introduced and applied to the physical design of latched comparators and A/D converter building blocks. In the following examination, post-layout simulation results are discussed and compared with measurement of the A/D circuits that were fabricated in a 0.35 μm digital CMOS process. It is shown in this paper that different circuit layout styles can result in significant differences in circuit performance. Additionally, it is shown that the layout-related performance variability is attributed to statistical processing variations.

Design and optimization of CMOS RF power amplifiers

A CMOS radio-frequency power amplifier including on-chip matching networks has been designed in a 0.6-/spl mu/m n-well triple-metal digital CMOS process, and optimized using a simulated-annealing-based custom computer-aided design tool. A compact inductor model enables the incorporation of parasitics as an integral part of the parasitic-aware design and CAD optimization; low-Q metal3 spiral inductors are used in the input and output matching networks. A 3-V 85-mW balanced fully integrated Class-C power amplifier with a measured drain efficiency of 55% at 900 MHz has been designed, optimized, integrated, and tested.

Novel self-error-correction pulse width modulator for a class D hearing instrument amplifier

The authors propose a pulse width modulator (PWM) for a hearing instrument (hearing aid) class D amplifier with emphases on low external component count, low cost, and low voltage and micropower operation. The PWM is based on a novel master–slave architecture that features a self-error-correction mechanism. This mechanism tunes the zero-input PWM output to 50% duty cycle, thereby reducing the output DC bias current of the amplifier; expensive post-fabrication calibration or trimming is unnecessary. The PWM is readily realised in a low-cost digital CMOS process and the input AC coupling capacitor is realised on-chip, reducing the external component count. The high matching requirement of the master and slave circuits is reduced by employing a novel switching methodology that periodically interchanges the critical (to matching) subcircuits of the master and slave circuits, without disrupting the continuous operation of the PWM. Computer simulations and measurements on prototype ICs show that the zero-input PWM output duty cycle error is ≤ 2%, well within specifications, i.e. the DC output bias current (for RL = 600 Ω) is Io = 83 µA at VDD = 2.5 V (or equivalent to Io = 22 µA at VDD = 1.3 V). The PWM circuit draws 25 µA at VDD = 2.5 V (or equivalent to 10 µA at VDD = 1.3 V.

Fully differential switched-current memory cell with low charge-injection errors

A fully differential switched-current memory cell with low charge-injection errors is proposed. The cell uses constant-voltage switching to obtain signal-independent charge injection, which is rejected using suitable differential structures. The cell is designed using a 0.35 µm digital CMOS process. Simulation results of the cell with a clock frequency of 13 MHz and with input signal amplitudes nearly as high as the bias current (600 µA) show a total harmonic distortion of –66 dB, a current transfer error of less than 0.4% and a signal-to-noise ratio of 60 dB.

A supply-noise-insensitive CMOS PLL with a voltage regulator using DC-DC capacitive converter

A 500-MHz supply-noise-insensitive CMOS phase-locked loop (PLL) with a voltage regulator using a capacitive dc-dc converter (VRCC) achieves a jitter level of 30-ps RMS for quiet supply, and 42-ps RMS for 600-mV supply noise, with a locking range of 110 to 850 MHz. The worst-case power supply noise rejection (PSNR) using the VRCC shows -45 dB in the mid-frequency band. The circuit is fabricated in a 0.35-/spl mu/m 3.3-V standard digital CMOS process and occupies 2.3 mm/sup 2/. The power consumption at 3.3 V including buffer is 42 mW at 500 MHz.

A CMOS self-calibrating frequency synthesizer

A programmable phase-locked-loop (PLL)-based frequency synthesizer, capable of automatically adjusting the nominal center frequency of the voltage-controlled oscillator (VCO) to an optimum value is described. In fully integrated PLLs, the VCO output frequency should be tunable over a wide range of frequencies, covering the desired range of the synthesizer output frequencies, for all processing variations and operating conditions. A wide tuning range realized by making the VCO gain K/sub o/ large has the unwanted effect of increasing the phase noise at the output of the VCO, and hence the PLL as well. In this work, the wide tuning range is realized by digital control, with process variability managed through self-calibration. The PLL is only required to pull the oscillator output frequency to account for the digital quantization, temperature variations, and some margin. This allows the K/sub o/ to be small, with better noise performance resulting. The prototype self-calibrating frequency synthesizer, capable of operating from 80 MHz to 1 GHz, demonstrates a measured absolute jitter of 20-ps rms at 480-MHz operating frequency. The prototype IC is fabricated in a 0.35-/spl mu/m 3-V digital CMOS process.

A novel expansible current-mode sorter

A novel expansible current-mode sorter based on magnitude is proposed. Its structure is simple and flexible. It can be cascaded easily for more inputs. At present, the sorter has been successfully fabricated in 1 µm standard digital CMOS processes. Experimental results show that the sorter has good performance.

Widely programmable high-frequency continuous-time filters in digital CMOS technology

We present design considerations for programmable high-frequency continuous-time filters implemented in standard digital CMOS processes. To reduce area, accumulation MOS capacitors are used as integrating elements. The filter design problem is examined from the viewpoint of programmability. To allow frequency scalability without deterioration of noise performance and of the frequency response shape, we employ a technique called "constant-capacitance scaling," which assures that even parasitic capacitances remain invariant when transconductors are switched in and out of the filter. This technique is applied to the design of a programmable fourth order Butterworth continuous-time filter with a bandwidth programmable from 60 to 350 MHz implemented in a 0.25-/spl mu/m digital CMOS process. The filter has a dynamic range of 54 dB, dissipates 70 mW from a 3.3-V supply, and occupies an area of 0.15 mm/sup 2/.

A 1.3 GHz low-phase noise fully tunable CMOS LC VCO

This paper presents a low-phase noise CMOS LC-VCO, in which a complete compensation of the component spread, due to process variations, can be done. The LC tank is made of a metal-oxide-silicon varactor and a bondwire and a spiral inductor in series. The trade-off between VCO gain variations and phase noise is introduced. The measurements performed on a prototype, powered by a 2-V supply, realized in a digital CMOS process, are presented. The oscillation frequency can be varied in the range 1.1-1.45 G-Hz. The measured phase noise at an offset of 600 kHz from a 1.3-GHz carrier is -119 dBc/Hz, with 6-mA current consumption.

A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line

This paper describes a CMOS time-to-digital converter (TDC) integrated circuit utilizing tapped delay lines. A technique that allows the achievement of high resolution with low dead-time is presented, The technique is based on a Vernier delay line (VDL) used in conjunction with an asynchronous read-out circuitry. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. A test circuit fabricated in a standard 0.7-/spl mu/m digital CMOS process is presented. The TDC contains 128 delay stages and achieves 30-ps resolution, stabilized by the DLL, with the accuracy exceeding /spl plusmn/1 LSB. Test results show that even higher resolutions can be achieved using the VDL method, and resolutions down to 5 ps are demonstrated to be obtainable.