Novel self-error-correction pulse width modulator for a class D hearing instrument amplifier

Abstract

The authors propose a pulse width modulator (PWM) for a hearing instrument (hearing aid) class D amplifier with emphases on low external component count, low cost, and low voltage and micropower operation. The PWM is based on a novel master–slave architecture that features a self-error-correction mechanism. This mechanism tunes the zero-input PWM output to 50% duty cycle, thereby reducing the output DC bias current of the amplifier; expensive post-fabrication calibration or trimming is unnecessary. The PWM is readily realised in a low-cost digital CMOS process and the input AC coupling capacitor is realised on-chip, reducing the external component count. The high matching requirement of the master and slave circuits is reduced by employing a novel switching methodology that periodically interchanges the critical (to matching) subcircuits of the master and slave circuits, without disrupting the continuous operation of the PWM. Computer simulations and measurements on prototype ICs show that the zero-input PWM output duty cycle error is ≤ 2%, well within specifications, i.e. the DC output bias current (for RL = 600 Ω) is Io = 83 µA at VDD = 2.5 V (or equivalent to Io = 22 µA at VDD = 1.3 V). The PWM circuit draws 25 µA at VDD = 2.5 V (or equivalent to 10 µA at VDD = 1.3 V.