Design of Digital CMOS Neuromorphic IC with Current-starved SRAM Synapse for Unsupervised Stochastic Learning

Abstract

This paper proposes a current-starved SRAM circuit for use as a synapse to support a biological learning of spike-timing dependent plasticity. If the driving strength of SRAM is limited both when writing a new state and restoring the previous state, then programming the opposite synaptic weight requires several densely-repeated write operations. The synapse takes only stochastically-meaningful stimuli for training, and rejects random and noisy inputs; as a result it achieves successful learning even with binary SRAM. The proposed synapse is applied to a three-layer neuromorphic network of spiking neurons that includes a receptive synaptic array and a projective synaptic array. The network is designed with a 28-nm digital CMOS process. Applying an unsupervised learning to only the projective synapses with the receptive synapses fixed at randomly given, the network successfully memorizes multiple overlapped image patterns and recalls the trained patterns if the images are distorted.