Digital Circuit Design Research Articles

Cluster-based test vector re-ordering for reduced power dissipation in digital circuits

Optimizing testing power is a paramount concern in modern digital circuit design, particularly as the intricacy of circuits continues to rise. This issue becomes even more pronounced with the scaling down of feature sizes due to advancements in process technology. The increase in testing power dissipation, beyond the regular operational state, raises red flags for both designers and test engineers. This paper introduces a novel cluster-based approach, shedding light on the efficient reordering of test vectors to mitigate the heightened switching activity. This technique aims to reduce the power consumption during testing, while still ensuring efficient error detection, maintaining the test period, and preserving the original order of the scan chain. Importantly, this reordering method does not introduce any additional area or test time overhead, minimizing the risks associated with these factors. The potential impact of this approach is demonstrated through concrete examples drawn from ISCAS’89 benchmark circuits. The results showcase a notable 11% reduction in switching activity, all while preserving fault coverage levels.

An efficient GNRFET-based circuit design of ternary half-adder

Attaining low energy consumption in digital circuits design is a main task for designers because emerging applications are based on batteries and face limited-energy. Designing digital circuits with application to multiple-valued logic (MVL) and graphene nanoribbon field-effect transistor (GNRFET) provides a huge improvement in energy consumption. In this regard, this paper presents a novel ternary Half-Adder (THA) implemented with metal-oxide semiconductor (MOS)-type GNRFET. In the proposed THA, the Sum circuit is based on a combination of 3:1 ternary multiplexer, unary operators, and two supply voltages (dual-VDD), and the Carry circuit is based on unary operators, pass-transistor logic, and dual-VDD. The proposed THA is simulated using the 32-nm MOS-type GNRFET technology node at 0.9 V supply voltage in the HSPICE simulator. The proposed THA reduces the transistors count by 5.71–26.67% compared to the previously published THA circuits available in the literature, which are similar to the proposed THA from the design approach point of view. It is concluded from the simulation results that the proposed THA improves the power and energy consumptions by 83.33–91.41% and 66.38–82.27%, respectively. Moreover, the proposed THA is also designed and simulated using the Stanford 32-nm carbon nanotube field-effect transistor (CNTFET) technology. The proposed MOS-type GNRFET-based THA reduces the power and energy consumptions by 84.79% and 68.03%, respectively, and increases the delay by 2.12 × compared to its CNTFET-based counterpart. Moreover, the proposed CNTFET-based THA offers the second-lowest delay and power and the third-lowest energy compared to other existing CNTFET-based THA circuits.

Variable Ordering in Binary Decision Diagram Using Spider Monkey Optimization for Node and Path Length Optimization

Binary Decision Diagrams (BDDs) are an important data structure for the design of digital circuits using VLSI CAD tools. The ordering of variables affects the total number of nodes and path length in the BDDs. Finding a good variable ordering is an optimization problem and previously many optimization approaches have been implemented for BDDs in a number of research works. In this paper, an optimization approach based on Spider Monkey Optimization (SMO) algorithm is proposed for the BDD variable ordering problem targeting number of nodes and longest path length. SMO is a well-known swarm intelligence-based optimization approach based on spider monkeys foraging behavior. The proposed work has been compared with other latest BDD reordering approaches using Particle Swarm Optimization (PSO) algorithm. The results obtained show significant improvement over the Particle Swarm Optimization method. The proposed SMO-based method is applied to different benchmark digital circuits having different levels of complexities. The node count and longest path length for the maximum number of tested circuits are found to be better in SMO than PSO.

Efficient Error Estimation for High-Level Design Space Exploration of Approximate Computing Systems

This article presents an error estimation technique for a data-flow graph (DFG) representation of an approximate computing (AC) circuit. The technique, which may be used during the high-level design of digital circuits, estimates error metrics for the outputs of the approximate circuit. The proposed technique receives as an input, output error characterizations of arithmetic modules in a high-level library. The error modeling of a library module is accomplished by dividing the input (operand) ranges into intervals and then characterizing the output error for different combinations of these input intervals. Subsequently, the error for each combination is stored in a lookup table (LUT). The module error models are integrated into a design space exploration (DSE) framework to evaluate different combinations of exact and approximate realizations of various operations in the DFG. The DSE, which performs error calculation and propagation from inputs to outputs of the target DFG, may be used to explore trade-offs between the output error and other design metrics of the approximate circuit, e.g., energy efficiency. The efficacy of the proposed method is assessed for three image processing benchmarks. Results for these benchmarks demonstrate that the framework can efficiently generate the Pareto frontier (PF) in the trade-off space of accuracy versus energy efficiency for the targeted benchmarks. Compared to a purely simulation-based exploration, the proposed technique provides an average of 92 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> speed improvement.

Design of High-Speed Area-Efficient VLSI Architecture of 32-Bit Three-Operand Binary Adder

Abstract: Adders are one of the most widely used digital components in digital integrated circuit design. With the advances in technology, the design that offers either high speed, low power consumption, less area, or a combination of them is designed. There are various processes performed by the digital circuits among which arithmetic operations are prominent. Three-operand binary adder is the basic functional unit to perform the modular arithmetic in various cryptography and pseudorandom bit generator (PRBG) algorithms. Carry save adder (CS3A) is the widely used technique to perform the three-operand addition. However, the ripple carry stage in the CS3A leads to a high propagation delay. Moreover, a parallel prefix two-operand adder such as Han-Carlson (HCA) can also be used for three-operand addition, significantly reducing the critical path delay at the cost of additional hardware. Hence, a new high-speed and area-efficient adder architecture is designed using pre-compute bitwise addition followed by carry prefix computation logic to perform the three-operand binary addition that consumes substantially less area, low power, and drastically reduces the adder delay. To design a faster computing system with less hardware we require some other architecture. The proposed architecture will reduce the area as well as the delay by replacing the Han-Carlson adder with the Ladner fisher adder in a Highspeed area-efficient three-operand binary adder. The proposed architecture is synthesized with the zynq-7000 library. The proposed architecture reduces the LUT count and delay by 20 and 0.4 nanoseconds respectively. By using these synthesis results, we noted the performance parameters like the number of LUTs and delay. We compared the adders in terms of LUTs (represents area) and delay value

Bottom-Up and Top-Down Approaches for the Design of Neuromorphic Processing Systems: Tradeoffs and Synergies Between Natural and Artificial Intelligence

While Moore's law has driven exponential computing power expectations, its nearing end calls for new avenues for improving the overall system performance. One of these avenues is the exploration of alternative brain-inspired computing architectures that aim at achieving the flexibility and computational efficiency of biological neural processing systems. Within this context, neuromorphic engineering represents a paradigm shift in computing based on the implementation of spiking neural network architectures in which processing and memory are tightly co-located. In this paper, we provide a comprehensive overview of the field, highlighting the different levels of granularity at which this paradigm shift is realized and comparing design approaches that focus on replicating natural intelligence (bottom-up) versus those that aim at solving practical artificial intelligence applications (top-down). First, we present the analog, mixed-signal and digital circuit design styles, identifying the boundary between processing and memory through time multiplexing, in-memory computation, and novel devices. Then, we highlight the key tradeoffs for each of the bottom-up and top-down design approaches, survey their silicon implementations, and carry out detailed comparative analyses to extract design guidelines. Finally, we identify necessary synergies and missing elements required to achieve a competitive advantage for neuromorphic systems over conventional machine-learning accelerators in edge computing applications, and outline the key ingredients for a framework toward neuromorphic intelligence.

Design &amp; Implementation of Approximate 7:2 Compressor Based 16-bit Dadda Multiplier using Verilog

Now a days the technology is growing day by day with faster rate. Particularly the usage of electronics is increasing in wide range of ways depending on their intended purpose and preferences. In this regard multipliers are playing a vital role because they allow us to perform complex arithmetic operations involving large numbers more efficiently. Instead of performing a series of addition or subtraction operations, a multiplier allows us to perform the operation in a single step within no time that is the challenge of today’s world. So in addition to being more efficient, multipliers also have practical applications in fields such as engineering, computer science, and cryptography also used , for example, in the design of digital circuits and in the encryption and decryption of data. Overall, multipliers playing an important role in mathematics and its applications and are essential tools for performing complex computations efficiently. Compressors play a vital role in realizing the high speed multipliers. In error resilient applications such as Image processing, Multimedia and Matrix multiplication the approximate computing is used, which provides meaningful results faster with lower power consumption. In previous work the compressors are designed using the full adders which provides accurate results. The 4:2 and 5:2 approximate compressors are then introduced with 18% delay reduction and ADP reduction up to 52%. Now the further work concentrated on the implementation of 7:2 Approximate Compressor based multiplier, to further enhance the performance of multipliers. The proposed design will be expected to provide maximum extent of reduction in area, delay or power consumption and achieves improvement in terms of speed as compared to the 4:2 and 5:2 compressor based approximate multiplier.

Components to Support Choice in Self-Timed Asynchronous Design Flows

The design of digital circuits on recent technologies brings several challenges, among which robustness to variations stands out. Variation sources are multiple, and the evolution of integrated circuit fabrication techniques increases the number and relevance of such sources, and the complexity of ensuring circuit robustness against them. Some design paradigms naturally counter variations of one or more types. Asynchronous self-timed design is one such paradigm that can provide robustness to process, voltage, temperature, ageing and IR drop variations, to cite some of the main types. This paper proposes an enhancement to the Pulsar environment, a recently proposed open source automated flow for the design of self-timed clockless circuits.The six components proposed here enable describing choices and decisions on the flow of data tokens inside asynchronous circuits.Design capture in Pulsar can then employ these. To implement the abstract (synthesis-enabled) components, the paper also bringsthe proposal of the handshaking mutex, a versatile complex gate that eases the design of probe and arbiter, the two most complex among the new components. Results demonstrate the new version of Pulsar is more powerful than the previous, baseline, version, enabling the design capture and the automated synthesis steps of more complex asynchronous self-timed circuits. They also indicate the handshaking mutex operates correctly, and with a good level of attested fairness.

Testability design of memristive digital circuits based on Knowm memristor

A multi-function memristive logic test unit based on Knowm memristor is designed and implemented to the memristive digital circuits testability design in this article. The single fault memristive digital circuit is analyzed, Boolean difference algorithm is applied to the memristive digital circuits to generate test patterns and determine the location of the fault nodes. The multi-function memristive logic test unit can realize different functions, combining Boolean difference to solve the problem of uncertain faults with the same test patterns, and improve the controllability and observability of memristive digital circuits. It is a new exploration in testability design of memristive digital circuits, which provides new ideas and development directions, and lays a foundation for the research on the testability design of multi fault memristor digital circuits.

RECURSIVE TERNARY-BASED ALGORITHM FOR COMPUTING PRIME IMPLICANTS OF MULTI-OUTPUT BOOLEAN FUNCTIONS

The problem of computing the set of prime implicants to represent a Boolean function is a classical problem that is still considered a running problem for research because all known approaches have limitations. The article reviews existing methods for computing prime implicants and highlights their limitations, particularly for multi-output functions and limited scalability due to the growth in memory required to complete the computation. Then it proposes a recursive ternary-based minimization algorithm to compute the prime implicants of multi-output Boolean functions. The algorithm is based on the concept of Programmable Logic Array (PLA) tables, which provide a structured and efficient representation of Boolean functions. The algorithm takes advantage of the ternary logic system to efficiently compute the prime implicants while maintaining scalability for large and complex functions, which has significant implications for digital circuit design and optimization.

A Memristive-Based Design of a Core Digital Circuit for Elliptic Curve Cryptography

The new emerging non-volatile memory (NVM) devices known as memristors could be the promising candidate for future digital architecture, owing to their nanoscale size and its ability to integrate with the existing CMOS technology. The device has involved in various applications from memory design to analog and digital circuit design. In this paper, a combination of memristor devices and CMOS transistors is working together to form a hybrid CMOS-memristor circuit for XAX- Module, a core element used as digital circuit for elliptic curve cryptography. The proposed design was implemented using Pt/TaOx/Ta memristor device and simulated in Cadence Virtuoso. The simulation results demonstrate the design functionality. The proposed module appears to be efficient in terms of layout area, delay and power consumption since the design utilizes the hybrid CMOS/memristor gates.

Analytical Delay Modeling for a Sub-Threshold Cell Circuit with the Inverse Gaussian Distribution Function

Considering that power consumption (PC) is an extremely important indicator in digital circuit design, lower PC has always been our pursuit. PC and power supply voltage are positively correlated, and in this case, we must reduce the operating voltage of the circuit. However, as the voltage continues to decrease, various secondary effects and process variations become increasingly influential, making the delay distribution and its statistical characteristics more difficult to predict. In this paper, an inverse Gaussian distribution is used to model the propagation delay. Taking into account the local process variation, the multi-input delay analytical expression is derived according to the sub-threshold current formula to accurately predict the distribution and statistical characteristics of the delay, and the delay is obtained by calculation instead of Monte Carlo simulation, which greatly reduces the simulation time. The accuracy of the delay expression and delay distribution have been tested under 22 nm FDSOI technology and good results were obtained with operating voltages from 0.20 V to 0.30 V, in which the mean error of the delay is approx. 1.5%, the variance error is approx. 4.3%, and the error of the cumulative distribution function is approx. 2%.

Libretto: An Open Cell Timing Characterizer for Open Source VLSI Design

We propose an open source cell library characterizer. Recently, free and open-sourced silicon design communities are attracted by hobby designers, academies and industries. These open-sourced silicon designs are supported by free and open sourced EDAs, however, in our knowledge, tool-chain lacks cell library characterizer to use original standard cells into digital circuit design. This paper proposes an open source cell library characterizer which can generate timing models and power models of standard cell library.

Infrared Image Pre-Processing and IR/RGB Registration with FPGA Implementation

Infrared imaging sensors are frequently used in thermal signature detection applications in industrial, automotive, military and many other areas. However, advanced infrared detectors are generally associated with high costs and complexity. Infrared detectors usually necessitate a thermoelectric heater–cooler for temperature stabilization and various computationally complex preprocessing algorithms for fixed pattern noise (FPN) correction. In this paper, we leverage the benefits of uncooled focal plane arrays and describe a complete digital circuit design for Field Programmable Gate Array (FPGA)-based infrared image acquisition and pre-processing. The proposed design comprises temperature compensation, non-uniformity correction, defective pixel correction cores, spatial image transformation and registration with RGB images. When implemented on Xilinx Ultrascale+ FPGA, the system achieves a throughput of 30 frames per second using the Fraunhofer IMS Digital 17 μm QVGA-IRFPA with a microbolometer array size of 320 × 240 pixels and an RGB camera with a 1024 × 720 resolution. The maximum ratio of the standard deviation to the mean of 0.35% was achieved after FPN correction.

Novel multiplexer circuit design in quantum-dot cellular automata technology

The QCA technology is a strong contender for replacing CMOS technology in the design of nanoscale digital circuits. The goal of this paper’s design is to increase the performance of the multiplexer (MUX) circuit. The design strategy is using a cost-effective architecture and path-planning design, which can reduce design costs. This paper presents an efficient circuit for 2-to-1 QCA MUX. Then, two circuits including 4-to-1 and 8-to-1 QCA MUX circuits are developed using this 2-to-1 QCA MUX circuit. The functionality of these circuits is investigated using QCADesigner tool version 2.0.3. The designed 2-to-1 QCA MUX circuit has 0.5 clock cycles delay, 0.01μm2 area and 15 cells. Moreover, the suggested 4-to-1 (8-to-1) QCA MUX circuit has 53 (163) cells, 0.06 (0.18) μm2 area and 1 (3.75) clock cycles delay. The energy dissipation (Area-delay cost) of the proposed 2-to-1, 4-to-1, and 8-to-1 MUX at 1oK is 8.91 mev (0.04), 17.9 mev (0.96), and 39.3 mev (8.82), respectively. The comparison results demonstrate that the designed circuits provide benefits compared to other MUX circuits.

Fully fixed-point integrated digital circuit design of discrete memristive systems

In this paper, the fully fixed-point digital integrated circuits of discrete memristive systems are designed with very low circuit area cost, where the two-stage pipeline and multi-cycle architecture is employed. Firstly, the mathematical models of the discrete memristor and a memristor chaotic map are presented and dynamics are analyzed. Secondly, data flow design is carried out and the feasibility of the fixed-point model is discussed, which provides a foundation for the further circuit design. Thirdly, different architectures are designed and we get the optimal results. As a result, gate area of the discrete memristor is 40288 μm2 and the equivalent gate counts are 4588, while gate area of the discrete memristor map is 40424 μm2 and the equivalent gate counts are 4604. Moreover, a chaotic pseudo random sequence generator is designed and the NIST test is passed. It provides the foundation for the further applications of the discrete memristor and discrete memristor chaotic systems.

Implementation of Energy Effective Error Resistant Adders and Multipliers in Image Denoising Applications

The design of digital VLSI circuits must take energy efficiency into consideration. Reducing the circuit’s power consumption, which has been a major issue since 2000, would increase the necessity for energy efficiency. Error-tolerant systems heavily rely on approximate computation methods to increase power efficiency. The key factors of the system’s overall power consumption and area computation are adders and multipliers, which are also crucial in approximate computing. High energy-efficiency adders can be used to create additional multipliers. In order to dramatically minimize power consumption, this work builds and implements 8×8 Dadda multipliers using 1 bit approximation adders. Calculation is sped up by using the Dadda multiplier. In turn, by reducing propagation latency, the suggested design lowers power consumption in digital CMOS circuitry. The proposed multiplier design with approximate adders, which was created in Verilog HDL, simulated in FPGA, and synthesized in FPGA platform, is implemented on an ASIC platform using Cadence 90 nm Technology. The Gaussian filter additionally employs the proposed Dadda multiplier for picture denoising in approximation adder-based image processing applications.

IEEE SSCS Leuven Student Chapter Hosts Distinguished Lecturer Prof. Tony Tae-Hyoung Kim From NTU in Singapore [Chapters

On 21 November 2022, the IEEE Solid-State Circuits Society (SSCS) Leuven Student Chapter hosted a technical talk given by Prof. Tony Tae-Hyoung Kim at KU Leuven, Belgium. Kim received his M.S. degree from Korea University in Seoul, South Korea, and his Ph.D. degree from the University of Minnesota in Minneapolis. He is currently an associate professor at Nanyang Technological University (NTU) in Singapore and mainly performs research in the field of computing in memory (CIM) and low-power and high-performance digital, mixed-mode, and memory circuit design. In 2022–2023, he was elected as a distinguished lecturer for the SSCS.

Design of Area efficient comparator architecture using 5T XOR GATE

The use of comparators in computation-based designs is extensive, making optimization crucial. While some comparator designs use dynamic logic to achieve low-power consumption, the limitations of low-speed and poor-noise margin make this approach challenging. The proposed comparator design offers a new solution that is both area-efficient and has a high operating speed while consuming low-power. It was designed using 180nm technology in Tanner Tool, and its results were observed. Overall, this work presents a promising new solution for optimizing digital comparators and improving the efficiency and speed of computation-based designs. This work presents a new solution for optimizing N-bit digital comparators in terms of area, power, and speed. The proposed comparator structure is a clever design that consists of two crucial modules - the comparison evaluation module (CEM) and the final module (FM). The CEM is responsible for evaluating the comparison, and it uses a regular structure of repeated logic cells to implement a parallel prefix tree structure. This approach is independent of input operand bit widths, which makes it highly versatile and adaptable to different applications. The FM, on the other hand, validates the final comparison based on the results obtained from the CEM. This ensures that the final output is accurate and reliable. By utilizing these two modules, the proposed comparator structure is able to achieve high-precision comparisons while maintaining a relatively simple and efficient design. Overall, this comparator structure is a promising development in the field of digital circuit design, and it has the potential to improve the performance and reliability of a wide range electronic systems.

Design and analysis of ternary delay flip-flop implemented with carbon nanotube field effect transistor

Flip-flops serve as fundamental memory storage elements in digital circuits, and their efficiency significantly affects overall circuit performance. The aim of this study is to create a D flip-flop based on ternary logic and evaluate its performance in comparison to flip-flops that have already been designed. The proposed D flip-flop design leverages Carbon Nanotube Field Effect Transistors (CNTFETs). CNTFETs offer unique properties that can enhance the speed and power efficiency of flip-flop design. To evaluate the performance of the proposed design, it was simulated using the HSPICE simulator with a 32 nm Stanford CNTFET model. The simulation parameters include a power supply voltage of 0.9 volts and an operating frequency of 1 GHz. These specific settings allow researchers to analyze the behavior and performance of flip-flops under realistic operating conditions. By comparing the simulation results of the proposed D flipflop with the performance of previously designed flip-flops, the improvements are assessed in terms of the speed and power consumption. The simulation results provide valuable insights into the efficiency, reliability, and responsiveness of the proposed design. The findings of this research contribute to the advancement of digital circuit design by introducing a novel D flip-flop based on ternary logic and CNTFET technology. The goal is to enhance the overall performance efficiency of digital circuits, particularly in applications where D flip-flops are used as building blocks such as shift registers.