Digital Attenuator Research Articles

An S–K Band 6-Bit Digital Step Attenuator with Ultra Low Insertion Loss and RMS Amplitude Error in 0.25 μm GaAs p-HEMT Technology

An S–K Band 6-Bit Digital Step Attenuator with Ultra Low Insertion Loss and RMS Amplitude Error in 0.25 μm GaAs p-HEMT Technology

A 10-20 GHz 6-Bit High-Accuracy Digital Step Attenuator with Low Insertion Loss in 0.15 µm GaAs p-HEMT Technology.

In a beamforming circuit for a modern broadband phased-array system, high accuracy and compactness have received sufficient attention as they are directly related to side lobe level and fabrication cost, respectively. In order to meet the low phase error required, this paper proposed an ultra-broadband 6-bit digital step switched-type attenuator (STA) with capacitive/inductive compensation networks. Compared to the conventional methods, the proposed technique employs an improved simplified T-structure with capacitive compensation networks, which simultaneously achieves low insertion loss and high-accuracy amplitude/phase control. In addition, on-chip level shifting circuit is integrated to avoid complex control schemes. The strategy of prioritizing return loss is adopted to alleviate the performance degradation caused by impedance mismatch after cascade. As a proof-of-principle demonstration, a wideband 6-bit STA with core area of only 0.5 mm × 1.8 mm was designed via 0.15-micrometer GaAs pHEMT technology. It exhibits ultra-broadband operation with a 31.5 dB amplitude tuning range and a 0.5 dB tuning step. The insertion loss of the reference state is 4-5.3 dB. The return loss is better than 15 dB for all the 64 states. The RMS amplitude and phase errors are less than 0.2 dB and 2° over the 10 to 20 GHz.

A Multimode 28 GHz CMOS Fully Differential Beamforming IC for Phased Array Transceivers

A 28 GHz fully differential eight-channel beamforming IC (BFIC) with multimode operations is implemented in 65 nm CMOS technology for use in phased array transceivers. The BFIC has an adjustable gain and phase control on each channel to achieve fine beam steering and beam pattern. The BFIC has eight differential beamforming channels each consisting of the two-stage bi-directional amplifier with a precise gain control circuit, a six-bit phase shifter, a three-bit digital step attenuator, and a tuning bit for amplitude and phase variation compensation. The Tx and Rx mode overall gains of the differential eight-channel BFIC are around 11 dB and 9 dB, respectively, at 27.0–29.5 GHz. The return losses of the Tx mode and Rx mode are >10 dB at 27.0–29.5 GHz. The maximum phase of 354° with a phase resolution of 5.6° and the maximum attenuation of 31 dB, including the gain control bits with an attenuation resolution of 1 dB, is achieved at 27.0–29.5 GHz. The root mean square (RMS) phase and amplitude errors are <3.2° and <0.6 dB at 27.0–29.5 GHz, respectively. The chip size is 3.0 × 3.5 mm2, including pads, and Tx mode current consumption is 580 mA at 2.5 V supply voltage.

A six-digit digital attenuator working in the Sub6G band

A high-performance 3–6 GHz monolithic digital control attenuator chip is designed by using a 0.25 μm GaAs pHEMT process. The circuit adopts a cascade structure of 6 basic attenuation units, and 64 attenuation states are formed by controlling the on-state combination of different attenuation bits, and the attenuation structure connected in parallel to the attenuation resistor is given. The main simulation results show that the designed digitally controlled attenuator takes 0.5dB as the attenuation step, and the maximum attenuation value is 31.5 dB, an insertion loss of less than 2.55 dB, a return loss better than -15 dB, an attenuation accuracy of less than 0.5 dB for all states, an additional phase shift of less than -5°, a root mean square error better than 0.23 dB of attenuation amplitude, and chip size of 1.88 mm×1.0 mm.

Wideband pHEMT Digital Attenuator With Positive Voltage Control Driver

This letter presents a wideband 6-bit digital attenuator with positive voltage driving capability. The designed attenuator solves the problem that traditional pseudomorphic high-electron-mobility transistor (pHEMT) attenuators need negative voltage control so that it can be better compatible with CMOS control signals. The frequency-select attenuation parallel (FSAP) network is utilized to improve high-frequency attenuation fluctuation and enable wideband flat attenuation characteristics. Simultaneously, this letter creatively proposed the lossy dc-block (LDB) network, which not only completes the dc blocking effect but also improves the low-frequency resonance in high attenuation state. The attenuator is implemented in the GaAs 0.25- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> pHEMT process. It demonstrates a 31.5-dB attenuation range with an increment of 0.5 dB. In the range of 0.05–6 GHz, the measured results showed that the root-mean-square (rms) attenuation and the phase error are within 0.8 dB and 16°, respectively, the reference state insertion loss (IL) is better than 2.3 dB, and the return loss is better than 15 dB for all the 64 attenuation states; the total chip size is 2 mm2.

An S-Band-Receiving Phased-Array Antenna with a Phase-Deviation-Minimized Calibration Method for LEO Satellite Ground Station Applications

This study presents a new S-band-receiving phased-array antenna with a phase-deviation-minimized calibration method for the ground station of a low Earth orbit (LEO) satellite. The proposed antenna consists of 16 subarrays, 16 beamforming receiving RF modules (BF-RFMs), a power/control board, and a 16-way feed network. The subarray was achieved by joining two 8 × 1 arrays with a two-way power combiner. The 16-element antenna subarrays showed a gain of 16.1 dBi and a reflection coefficient of less than −10 dB from 2.12 GHz to 2.45 GHz. The BF-RFM, which consists of three low-noise amplifiers (LNAs), a power combiner, a phase shifter, and a digital attenuator, was designed and fabricated. The BF-RFMs were provided by the power/control board and showed a gain of 30.8 ± 0.8 dB, an amplitude root-mean-square (RMS) error from 0.25 dB to 0.28 dB, and a phase RMS error from 1.8° to 2.5° over the Rx frequency range. The arrangement procedures of the 16 BF-RFMs are presented to increase beam pointing accuracy at the desired angle. A commercial 16-way feed network was employed to combine all the output ports of the 16 BF-RFMs. The assembled antenna, which has dimensions of 1.58 m × 1.58 m × 0.2 m, was measured by partial and full scans in the near-field scanning system. The back-projected algorithm was employed to calibrate the antenna’s gain patterns in the partial scan. The implemented phased-array antenna had a gain greater than 28.14 dBi, sidelobe levels less than −17.1 dB, and beam pointing errors less than 0.07° over the beam pointing angle of −20~+20°. Based on the implemented antenna system, we conducted a field test using KOMPSAT-5, which is actually operating in South Korea, in order to verify the performance of the low Earth orbit (LEO) satellite ground station system.

A C/X/Ku/K-Band Precision Compact 6-Bit Digital Attenuator with Logic Control Circuits

This paper proposes a C/X/Ku/K band 6-bit digital step attenuator (DSA) which employs a variety of improved attenuation cells to achieve a wide bandwidth, stable amplitude variation, stable phase variation, and small area. In this paper, the improved T-type, π-type, and switched-path type topologies are analyzed theoretically and applied to different attenuation values to achieve the optimal attenuator performance. In addition, in order to reduce the complexity and to improve the stability of the overall radar system, the logic control circuit is integrated in the DSA chip in this paper. Finally, the proposed attenuator is implemented in 0.15μm GaAs technology, which has a maximum attenuation range of 31.5 dB with 0.5 dB steps. The proposed DSA exhibits a root-mean-square (RMS) attenuation error of less than 0.15 dB and an RMS phase error of less than 3°, at 4–24 GHz. The insertion loss (IL) and the area of the DSA are 4.3–4.5 dB and 1.5 mm × 0.4 mm, respectively. Benefiting from the improvements of the attenuation cells and the characteristic of GaAs technology with strong resistance to radiation and power processing capability, the proposed DSA is suitable for spaceborne radar systems.

A Wideband 6-Bit Digital Attenuator in a GaAs pHEMT MMIC

A low insertion loss, wideband 6-bit digital step attenuator is implemented in the 0.25-μm GaAs pHEMT process. Modified π- or T-type attenuator structures are adopted to expand the operation frequency bandwidth and reduce the insertion phase violation. Furthermore, the through-wafer via (TWV) is analyzed to reduce the influence of the parasitic effect on the high-frequency performance of the attenuator. The depletion mode single-gate switch transistors are used to control the on-off state of the attenuator, which provides low insertion loss and high isolation. The step of the attenuator is 0.5 dB, and the attenuation range is 31.5 dB. The measurement results show a maximum root mean square (RMS) attenuation error of 0.51 dB and RMS phase error of 6.6 degrees from DC-18 GHz. The chip area is 1.8 × 0.6 mm2.

A new extraction flow of the s mall‐signal s witch‐HEMT model based on the parasitic resistance scanning algorithm

Recent research interest in switch High Electron Mobility Transistor (HEMT) modeling revealed the special modeling requirement that is a parasitic capacitance shell surrounding the equivalent circuit. Despite the robust determination of parasitic capacitances, one still may face several problems when extracting a small-signal switch-HEMT model. Practical switch-HEMT test structures include different configurations of gate network with additional microstrip lines, large-value resistors, and via-holes. Ignoring parts of these networks results in unfavorable errors when comparing measured and simulated results. Another problem may arise when extracting the switch-HEMT equivalent circuit parameters from the measured S-parameters of the grounded gate test structures: obtained parasitic resistances can be exaggerated, resulting in negative values of intrinsic channel resistance (conductance). This paper presents a new switch-HEMT extraction flow intended to address the mentioned challenges. To eliminate an excessive gate inductance attributed to via-hole, we introduce a concept of the gate network de-embedding. A negative channel resistance (conductance) problem is handled by applying a new parasitic resistance scanning algorithm that allows finding the model parameter vector with reasonable positive values in the vicinity of the S-parameters modeling error minimum. Accurate S-parameters modeling results verify the proposed extraction flow. Obtained small-signal switch-HEMT models are validated by designing and manufacturing a 2 dB digital step attenuator section.

A Ku-Band Bi-Directional Transmit and Receive IC in 0.13 μm CMOS Technology

This paper presents a Ku-band transmit and receive IC in 0.13 µm CMOS technology for mobile satellite communication beamforming systems. A Ku-band transmit and receive IC is composed of a bi-directional amplifier, a 6-bit phase shifter, and a 6-bit digital step attenuator. The precise trimming bits are implemented in the phase shifter (2.8°) and digital step attenuator (0.5 and 1 dB) for the amplitude and phase error correction. The phase variation range of the phase shifter is 360° with a phase resolution of 5.625°. The attenuation range of 31.5 dB with an amplitude resolution of 0.5 dB is achieved. The gain of 2~5 dB and the input/output return losses of &gt;10 dB are achieved from 12 to 16 GHz. The chip size is 2.5 × 1.5 mm2 including bonding pads. The DC power consumption is 216 mW.

An S/C/X-Band 4-Bit Digital Step Attenuator MMIC with 0.25 μm GaN HEMT Technology

In this paper, a 4-bit digital step attenuator using 0.25 μm GaN HEMT technology for wideband radar systems is presented. A switched-path attenuator topology with resistive T-type attenuators and double-pole double-throw (DPDT) switches was used to achieve both low insertion loss and phase/amplitude error. The measured insertion loss of the reference state is 2.8–8.3 dB at DC-12 GHz. The input and output return loss are less than 12 dB at DC-12 GHz. An attenuation coverage of 30 dB with a least significant bit of 2 dB was achieved at DC-12 GHz. A root mean square (RMS) amplitude error of 1 dB and a phase error of 8.5° were achieved, respectively. The attenuator chip size is 2.45 mm × 1.75 mm including pads. To the best of the authors’ knowledge, this is the first demonstration of a GaN-based digital step attenuator.

Ultra wideband CMOS digital T-type attenuator with low phase errors

A proposed inductive-phase-compensation ultra wideband CMOS digital T-type attenuator design based on an analysis of minimising phase errors is presented in this letter. In a standard CMOS technology, the proposed attenuator is analytically demonstrated to have low phase errors due to the inductive-phase-compensation network. A design equation is inferred and a wide-band 4dB attenuation bit digital attenuator with low phase errors is designed as a test vehicle for the proposed approach.

Design Methodology for a Wideband, Low Insertion Loss, Digital Step Attenuator in SiGe BiCMOS Technology

This paper presents a wideband, low insertion loss, high attenuation range digital step attenuator (DSA) implemented using SiGe HBTs. In a switched-type topology, the off-state capacitances (COFF) in both reference and attenuation states cause different poles and zeros, which trigger amplitude and phase errors and limit the operating bandwidth. To achieve wide bandwidth, methods to relocate poles and zeros to the highest possible frequencies in both states are investigated. In the reference state, minimizing the size of the shunt switching transistors extends the bandwidth. In the attenuation state, switching in a capacitor at the base of an anti-parallel (AP) SiGe HBT pair series switch reduces the effective COFF, enhancing the bandwidth. The proposed techniques facilitate the realization of a 16-dB attenuator cell to support wide bandwidth and offer lower insertion loss than conventional cascaded 8-dB cell designs. Fabricated in 130-nm SiGe BiCMOS technology, the proposed DSA with an attenuation range of 31.5 dB in 0.5 dB steps operates from DC to 67 GHz and achieves an insertion loss lower than 7.8 dB. The RMS amplitude error is less than 0.4 dB above 1 GHz, while the RMS phase variation is less than 13.1∘.

15～45 GHz 고해상도 소형 분산형 디지털 감쇠기

This paper describes the design and measurement of a compact distributed digital attenuator using multi-state cells. The attenuator consists of four multi-state cells with different attenuation states. To improve linearity, a stacked-FET topology, in which four transistors are stacked, is applied to the parallel transistors of multi-state cells. In addition, grounded T-lines are inserted to the source of parallel transistors to compensate the phase error. The size of parallel transistors is optimized to implement a 0.5-dB attenuation step and to remove the coupling effect of the previously proposed compact distributed digital attenuator. The attenuator showed a measured 14-dB maximum attenuation range and 0.5-dB attenuation step in a frequency range of 15～45 GHz. The RMS amplitude error and RMS phase error were 0.1～1.4 dB and 1.7～4°, respectively.

A Fully Integrated S-Band Phase-Array Receiver in 0.13 μm CMOS SOI

In traditional phased-array T/R modules, front-end modules such as limiter, low-noise amplifier (LNA) and RF switch are generally implemented by independent devices, with low integration and high cost. This paper realizes the integration of all receiver functional modules in the 0.13[Formula: see text][Formula: see text]m CMOS SOI process, including RF switch, LNA with limiter, 6-bit digital controlled attenuator and phase shifter, and drive amplifier. The LNA integrates a limiting function, which can suffer 2[Formula: see text]W continuous wave. Fast charge–discharge circuit is applied to the low insertion loss RF switch, which greatly reduces the switching time. The phase shifter adopts a double balanced switch used for 180∘ phase shift, which significantly reduces the phase error. The measured channel gain is about 28[Formula: see text]dB with an NF about 2.3[Formula: see text]dB and an IP1 dB above [Formula: see text]14[Formula: see text]dBm. The state error of attenuator is less than [Formula: see text][Formula: see text]dB with step error less than [Formula: see text][Formula: see text]dB. The RMS phase error of phase shifter is less than 1.8 degrees. The fully integrated transceiver IC occupies an area of [Formula: see text][Formula: see text]mm2. This receiver draws only 128[Formula: see text]mA with a 3.3[Formula: see text]V power supply.

Syn-STELLAR: An EM/Power SCA-Resilient AES-256 With Synthesis-Friendly Signature Attenuation

Mathematically secure cryptographic algorithms leak meaningful side-channel information in the form of correlated power and electromagnetic (EM) signals, leading to physical side-channel analysis (SCA) attacks. Circuit-level countermeasures against power/EM SCA include a current equalizer, IVR, non-linear LDOs, enhancing protection up to 10M traces, and current-domain signature attenuation (CDSA), and randomized NL-LDO cascaded with arithmetic countermeasures achieved protection up to >1B. This work embraces the concept of analog CDSA but makes it easily scalable over technology nodes with digital-friendly current sources, digital control loop, and digital bleed path to increase the MTD from 10M to 250M (25x improvement, using a single digital countermeasure). Ring oscillator (RO) used as the bleed path to bypass encryption-dependent leakage acts as local negative feedback (LNFB). Besides, based on RO oscillation frequency, AES node voltage can be tuned at startup, PVT, or frequency variation. Thus, RO acts as integrated LNFB and global feedback for the digital signature attenuation circuit (DSAC). Another circuit technique, namely, the time-varying transfer function (TVTF), removes the requirement of dc bias in the current-domain equalizer (best switch capacitor-based countermeasure till date) to make it digital and utilizes switch cap-based circuit for time-domain obfuscation to achieve enhanced security. This work, namely, Syn-STELLAR: SYNthesis-friendly Signature aTtenuation Embedded crypto with Low-Level metAl Routing, combines both DSAC and TVTF techniques to achieve an MTD>1.25B for both EM and power SCA, which is 25% higher than the existing state of the art. The 65-nm CMOS test chip contains unprotected and both the protected (DSAC and DSAC-TVTF) parallel AES-256 implementation. This implementation is the first synthesis-friendly countermeasure, which converges two analog-type strong protections (signature attenuation and switched cap current equalizer) in a digital-friendly solution and achieves >1.25B MTD with power and area overheads comparable to previous circuit-level countermeasures.

전자전 다중 위협 재밍을 위한 멀티빔 송수신장치용 광대역 고출력 송수신모듈 개발

An eight-channel transmit/receive module (TRM) was designed for a wideband electronic warfare multiple threat jamming transceiver. In the system, the TRM amplifies a multijamming signal from a multibeam transceiver module and a small radio frequency (RF) signal from an antenna. In TX mode, it has an output power of more than 43 dBm for a continuous wave. In RX mode, it has a gain of more than 10 dB and noise figure of less than 5 dB. The voltage standing wave ratio is less than 2:1, and the TX and RX path isolation is 50 dBc or more. The RF signal amplitude and phase variation are less than 2 dB and 10°, respectively. True time delay and a digital attenuator are used to compensate for the signal amplitude and phase for each channel.

Design of 0~21 GHz wideband silicon-based digital attenuator with high accuracy

Design of 0~21 GHz wideband silicon-based digital attenuator with high accuracy

Development of digital BPM front-end conditioning circuit for BEPCII linac

Aiming to control the rising failure rate of electronics system for BEPC II linac’s beam position measurement, considering the physical design parameters of BEPC II and the requirements of band-pass sampling of BPM electronics ADC chip, a digital BPM RF front-end electronics with high isolation degree and good amplitude and phase consistency is designed. The digital BPM electronics system adopts MicroTCA 4.0 system architecture, takes FPGA as the main controller, and is designed based on EDA software. This paper mainly introduces RF power amplifier, digital adjustable attenuator and bandpass filter in RF front-end electronics module, as well as the laboratory and online test results. In the collision mode of BEPC II, positron beam was used to complete the electronic system online test, and the measurement accuracy of x-direction was about 38.46 μm, while that of y-direction was about 26.16 μm. The measurement accuracy and system stability of the proposed method are better than that of commercial analog BPM electronics module, and can meet the beam position measurement requirements of BEPC II linac.

A DC to 25 GHz 6‐bit digital attenuator based on 0.18 μm SiGe BiCMOS technology

A wideband, low phase variation 6-bit digital step attenuator (DSA) is presented. To further expand the operation bandwidth while keeping low attenuation and phase error, modified π/T-type attenuator structures are introduced. In the large attenuation unit, the modified π-type attenuator structure is adopted, which includes middle adjusting capacitance and bypass compensating capacitance. Moreover, the reduced T-type structure with bypass compensation capacitance is used in the small attenuation units. The influence of the introduced capacitance on various attenuation units is analyzed. To prove the effectiveness of the modified structure on extending the bandwidth, a DSA with a broad bandwidth of DC-25 GHz and low attenuation and phase error is realized in a 0.18 μm SiGe BiCMOS technology. The attenuation range of the attenuator is 31.5 dB with 0.5-dB step, which is controlled by 6 bits digital input. Its root-mean-square (RMS) attenuation error is lower than 0.3 dB, and the phase error (RMS) is below 4.9°. The insertion loss is lower than 11 dB, and the core area is 0.33 mm2.