Abstract
A low insertion loss, wideband 6-bit digital step attenuator is implemented in the 0.25-μm GaAs pHEMT process. Modified π- or T-type attenuator structures are adopted to expand the operation frequency bandwidth and reduce the insertion phase violation. Furthermore, the through-wafer via (TWV) is analyzed to reduce the influence of the parasitic effect on the high-frequency performance of the attenuator. The depletion mode single-gate switch transistors are used to control the on-off state of the attenuator, which provides low insertion loss and high isolation. The step of the attenuator is 0.5 dB, and the attenuation range is 31.5 dB. The measurement results show a maximum root mean square (RMS) attenuation error of 0.51 dB and RMS phase error of 6.6 degrees from DC-18 GHz. The chip area is 1.8 × 0.6 mm2.
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