Design Methodology for a Wideband, Low Insertion Loss, Digital Step Attenuator in SiGe BiCMOS Technology

Abstract

This paper presents a wideband, low insertion loss, high attenuation range digital step attenuator (DSA) implemented using SiGe HBTs. In a switched-type topology, the off-state capacitances (COFF) in both reference and attenuation states cause different poles and zeros, which trigger amplitude and phase errors and limit the operating bandwidth. To achieve wide bandwidth, methods to relocate poles and zeros to the highest possible frequencies in both states are investigated. In the reference state, minimizing the size of the shunt switching transistors extends the bandwidth. In the attenuation state, switching in a capacitor at the base of an anti-parallel (AP) SiGe HBT pair series switch reduces the effective COFF, enhancing the bandwidth. The proposed techniques facilitate the realization of a 16-dB attenuator cell to support wide bandwidth and offer lower insertion loss than conventional cascaded 8-dB cell designs. Fabricated in 130-nm SiGe BiCMOS technology, the proposed DSA with an attenuation range of 31.5 dB in 0.5 dB steps operates from DC to 67 GHz and achieves an insertion loss lower than 7.8 dB. The RMS amplitude error is less than 0.4 dB above 1 GHz, while the RMS phase variation is less than 13.1∘.