15～45 GHz 고해상도 소형 분산형 디지털 감쇠기

Abstract

This paper describes the design and measurement of a compact distributed digital attenuator using multi-state cells. The attenuator consists of four multi-state cells with different attenuation states. To improve linearity, a stacked-FET topology, in which four transistors are stacked, is applied to the parallel transistors of multi-state cells. In addition, grounded T-lines are inserted to the source of parallel transistors to compensate the phase error. The size of parallel transistors is optimized to implement a 0.5-dB attenuation step and to remove the coupling effect of the previously proposed compact distributed digital attenuator. The attenuator showed a measured 14-dB maximum attenuation range and 0.5-dB attenuation step in a frequency range of 15～45 GHz. The RMS amplitude error and RMS phase error were 0.1～1.4 dB and 1.7～4°, respectively.