Semiconductor-insulator Interface Research Articles

Electron Donating Functional Polymer Dielectrics to Reduce the Threshold Voltage of n‐Type Organic Thin‐Film Transistors

AbstractLow‐cost and high‐performance electronics based on synthetically simple materials are required to fuel the deployment of smart packaging and wearable electronics. Metal phthalocyanines (MPcs) are promising semiconductors for use in n‐type organic thin film transistors (OTFTs) but often require high operating voltages. The first silicon phthalocyanine‐based OTFT with a polymer dielectric is reported as an alternative to traditional metal oxide dielectrics. Incorporating poly(methyl methacrylate) (PMMA) as the dielectric successfully reduces the threshold voltage (VT) of bispentafluorophenoxy SiPc (F10‐SiPc) from 14.9V to 7.3V while retaining high mobility. Further reduction in VT is obtained by using copolymers and blends of PMMA and dimethylamino ethyl methacrylate (DMAEMA)‐containing polymers, where a higher molar fraction of DMAEMA leads to a consistent drop in VT to ‐0.7 V. The electron‐donating groups of the tertiary amines in the DMAEMA show clear interfacial doping of the semiconductor, reducing the voltage required to populate the dielectric/semiconductor interface with charge carriers and turn on the device. Blending trace amounts of DMAEMA‐containing copolymers with PMMA proves to be an effective strategy for reducing the VT while keeping the charge mobility high, unlike when using pure copolymers with elevated DMAEMA content. Time of flight secondary ion mass spectroscopy (ToF‐SIMS) and X‐ray photoelectron spectroscopy (XPS) demonstrate that the DMAEMA‐containing copolymer is floating to the surface of the PMMA blend at the dielectric–semiconductor interface, which explains the reduced VT. Synchrotron scanning transmission X‐ray microscopy (STXM) demonstrates that PMMA promotes a more edge‐on orientation of F10‐SiPc films, compared to the more face‐on orientation when deposited on the DMAEMA containing copolymer. This study demonstrates a straightforward process for designing dielectric polymers and their blends for the reduction in VT for n‐type OTFTs.

On the Properties of the Si-SiO2 Transition Layer in Multilayer Silicon Structures

Capacitance spectroscopy was used to study the capacitive-voltage characteristics of multilayer structures with a Si-SiO2 transition layer in Al-SiO2-n-Si type samples fabricated by the thermal oxidation of a semiconductor. It is shown that the inhomogeneous distribution of the density of surface states is a localized electroactive center at the very semiconductor-dielectric interface, due to over-barrier charge emission or thermal ionization of impurity centers.

Effects of source/drain electrode thickness on water-induced instability of laminated organic single-crystal field-effect transistors

Water is known to be the main cause of operational instability in organic electronic devices under ambient conditions. The water-induced hysteresis of lithography-friendly bottom-gate-bottom-contact-type organic field-effect transistors (FETs) with a laminated single-crystal channel was investigated using varying electrode thicknesses. As the amount of water in the air gap enveloped by the semiconductor layer and insulating substrate, adjacent to the electrode, increases, the mechanism dominating the hysteresis phenomenon shifted in the following order: (1) current increase owing to the decreasing charge-injection barrier because of a drain-induced change in the electrode work function, (2) current decrease because of the gate bias stress, and (3) current increase because of the gate enhancement effect owing to the dipole orientation of the water molecules penetrating the semiconductor-insulator interface. Changes in the electrode thickness had the same effect on the hysteretic behavior as the relative humidity of the experimental environment. Thus, this study provides a comprehensive understanding of the water-induced operational instability of laminated organic single-crystal FETs and should aid the realization of stable-operation organic devices, as well as foreign-molecule sensors, by controlling the electrode thickness.

Effect of structure on semiconducting properties of a small molecule n-type organic semiconductor: Phenyl-C61-butyric acid methyl ester

The fullerene-based derivative phenyl-C61-butyric acid methyl ester (PCBM) has attracted attention as an n-type transistor channel and an organic photovoltaic material due to its solution processability, stability, and high electron mobility. However, disorder in solution-processed PCBM thin films makes understanding of charge carrier transport mechanisms difficult. We have fabricated PCBM-based field effect transistors and improved device performance by reducing electron trapping at the dielectric–semiconductor interface and improving charge carrier injection. Single-wall carbon nanotubes were successfully integrated into conventional gold electrodes to improve injection efficiency. Meyer–Neldel behavior has been investigated in a study of charge carrier transport in PCBM thin films. Crystallization of PCBM was observed during the measurement. We find that charge carriers hop between molecules in mostly amorphous regions from 145 to 240 K. The transport is facilitated by the formation of more crystallized regions when samples are heated as high as 240 K.

Field-effect bulk mobilities in polymer semiconductor films measured by sourcemeters.

Semiconducting polymers inherently exhibit polydispersity in terms of molecular structure and microscopic morphology, which often results in a broad distribution of energy levels for localized electronic states. Therefore, the bulk charge mobility strongly depends on the free charge density. In this study, we propose a method to measure the charge-density-dependent bulk mobility of conjugated polymer films with widely spread localized states using a conventional field-effect transistor configuration. The gate-induced variation of bulk charge density typically ranges within ±1018cm-3; however, this range depends significantly on the energetic dispersion width of localized states. The field-effect bulk mobility and field-effect mobility near the semiconductor-dielectric interface along with their dependence on charge density can be simultaneously extracted from the transistor characteristics using various gate voltage ranges.

A Combined Theoretical and Experimental Approach to Deduce the Role of Dielectric Layer on Interface Trap Density in Single Crystal Organic Field‐Effect Transistors

AbstractA detailed understanding of charge transport at the interface is necessary to explore the potential of organic field‐effect transistors. This can be realized by adequately analyzing the trap states at the interface. In the present work, rubrene‐based organic field‐effect transistors have been fabricated with three different interfaces. The device properties are used along with a technology computer‐aided design to deduce the interface trap density quantitatively. The transfer characteristics are simulated using a double Gaussian density of states and fitted with experimental data by adding traps to the semiconductor dielectric interface. A typical transistor with SiO2 interface has shown an interface trap density of about ≈1016 cm−2, and it is reduced to 1014 cm−2 when poly(methyl)methacrylate or polystyrene is coated on SiO2 interface, attributed to the surface passivation. This approach provides a simple and accurate way to estimate the interfacial traps and offers the possibility to tune the device architecture and performance.

Nonlinear Optical Imaging of Carrier Transport at the Semiconductor-Insulator Interface in Organic Field-Effect Transistors

Organic field-effect transistors (FETs) are witnessing a revolution in their performance, in part, due to a reduction in contact resistance, and through controlled morphology of the organic semiconducting film. Another major consideration is the role of the dielectric layer in dictating transport properties. The transient electric-field-induced second-harmonic generation (EFISHG) technique allows visualization of carrier dynamics in the channel region of a FET by capturing the movement of the induced dielectric polarization. A microscopic imaging system using a broadband femtosecond laser and a pulse compensation arrangement is constructed for imaging transient EFISHG from organic FETs by synchronized laser and voltage pulses. By varying the dielectric layer in organic FETs comprising pentacene and a donor-acceptor conjugated polymer as semiconducting layers, we show that EFISHG images provide an accurate estimate of the carrier mobility along with providing insights into channel formation and the electric field distribution within the channel region. We further correlate the interface charging effects observed in EFISHG to the interface trap density obtained by capacitance-voltage and conductance-voltage from metal-insulator-semiconductor diodes.

Reducing charge noise in quantum dots by using thin silicon quantum wells

Charge noise in the host semiconductor degrades the performance of spin-qubits and poses an obstacle to control large quantum processors. However, it is challenging to engineer the heterogeneous material stack of gate-defined quantum dots to improve charge noise systematically. Here, we address the semiconductor-dielectric interface and the buried quantum well of a 28Si/SiGe heterostructure and show the connection between charge noise, measured locally in quantum dots, and global disorder in the host semiconductor, measured with macroscopic Hall bars. In 5 nm thick 28Si quantum wells, we find that improvements in the scattering properties and uniformity of the two-dimensional electron gas over a 100 mm wafer correspond to a significant reduction in charge noise, with a minimum value of 0.29 ± 0.02 μeV/Hz½ at 1 Hz averaged over several quantum dots. We extrapolate the measured charge noise to simulated dephasing times to CZ-gate fidelities that improve nearly one order of magnitude. These results point to a clean and quiet crystalline environment for integrating long-lived and high-fidelity spin qubits into a larger system.

Not Just Surface Energy: The Role of Bis(pentafluorophenoxy) Silicon Phthalocyanine Axial Functionalization and Molecular Orientation on Organic Thin-Film Transistor Performance.

Understanding the effect of surface chemistry on the dielectric-semiconductor interface, thin-film morphology, and molecular alignment enables the optimization of organic thin-film transistors (OTFTs). We explored the properties of thin films of bis(pentafluorophenoxy) silicon phthalocyanine (F10-SiPc) evaporated onto silicon dioxide (SiO2) surfaces modified by self-assembled monolayers (SAMs) of varying surface energies and by weak epitaxy growth (WEG). The total surface energy (γtot), dispersive component of the total surface energy (γd), and polar component of the total surface energy (γp) were calculated using the Owens-Wendt method and related to electron field-effect mobility of devices (μe), and it was determined that minimizing γp and matching γtot yielded films with the largest relative domain sizes and highest resulting μe. Subsequent analyses were completed using atomic force microscopy (AFM) and grazing-incidence wide-angle X-ray scattering (GIWAXS) to relate surface chemistry to thin-film morphology and molecular order at the surface and semiconductor-dielectric interface, respectively. Films evaporated on n-octyltrichlorosilane (OTS) yielded devices with the highest average μe of 7.2 × 10-2 cm2·V-1·s-1 that we attributed to it having both the largest domain length, which were extracted from power spectral density function (PSDF) analysis, and a subset of molecules with a pseudo edge-on orientation relative to the substrate. Films of F10-SiPc with the mean molecular orientation of the π-stacking direction being more edge-on relative to the substrate also generally resulted in OTFTs with a lower average VT. Unlike conventional MPcs, F10-SiPc films fabricated by WEG experienced no macrocycle in an edge-on configuration. These results demonstrate the critical role of the F10-SiPc axial groups on WEG, molecular orientation, and film morphology as a function of surface chemistry and the choice of SAMs.

Magnetic Field Effect in Hydrogen‐Bonded Semiconductor‐Based Organic Field‐Effect Transistors

Herein, the magnetic field effect on the source–drain current of organic field-effect transistors with semiconductor layers made of H-bonded pigments is studied. In all devices, an external magnetic field reduces the source–drain current in the transistor. The magnetic field effect is independent of the direction of the applied magnetic field. The observed increase of the magnetoresistance seems to originate from the used semiconductor or the semiconductor–dielectric interface and is not influenced by the nature of the gate electrodes or the semiconductors’ deposition procedure (e.g., grain size, layer thicknesses, etc.). As all prepared devices do have single charge carrier nature, the formation of bipolarons is suggested to be responsible for the observed magnetic field effect. The presented experiments demonstrate that hydrogen-bonded semiconductors behave no different than their classical van der Waals-bonded fully conjugated semiconductors’ counterparts.

Fully solution-processed carbon nanotubes thin film transistors and PMOS inverters on glass substrate

We report fully solution-processed thin film transistors and PMOS inverters fabricated on glass substrates using single-walled carbon nanotubes (SWCNTs) as active semiconducting material. All the electrodes (gate, source, and drain) were inkjet-printed using silver (Ag) as conductive ink. Spin coated poly-4-vinylphenol dielectric was optimized in terms of thickness and heating conditions for solution-processed SWCNTs thin film transistors to achieve a mobility equal to 0.81 cm2 V−1s−1. We will show that, hole traps at the dielectric-semiconductor interface are responsible for the hysteresis in the transfer curve, and controlled by the different sweep rate of the gate field. Drain-current transients under different bias conditions were studied and the increase in current occurs due to slow polarizations of residual dipolar groups in the dielectric. The adopted technology has been exploited to fabricate a PMOS inverter and studied for high gain and noise margin values at the supply voltage, V DD = −40 V.

Electrically stimulated optical spectroscopy of interface defects in wide-bandgap field-effect transistors

Wide-bandgap semiconductors such as silicon carbide, gallium nitride, and diamond are inherently suitable for high power electronics for example in renewable energy applications and electric vehicles. Despite the high interest, the theoretical limit regarding device performance has not yet been reached for these materials. This is often due to charge trapping in defects at the semiconductor-insulator interface. Here we report a one-to-one correlation between electrically stimulated photon emission and the threshold voltage shift obtained from a fully processed commercial 4H-SiC metal-oxide-semiconductor field-effect power transistor. Based on this observation, we demonstrate that the emission spectrum contains valuable information on the energetic position of the charge transition levels of the responsible interface defects. We etch back the transistor from the reverse side in order to obtain optical access to the interface and record the emitted light. Our method opens up point defect characterization in fully processed transistors after device passivation and processing. This will lead to better understanding and improved processes and techniques, which will ultimately push the performance of these devices closer to the theoretical limit.

Unlocking performance potential of two-dimensional SnS2 transistors with solution-processed high-k Y:HfO2 film and semimetal bismuth contact

Two-dimensional (2D) tin disulfide (SnS2) is emerging as a viable channel material for high-performance field-effect transistors (FET) with high intrinsic mobility. To implement a high-performance two-dimensional SnS2 FET, high field-effect mobility (μFE), steep subthreshold swing (SS), high on-current value (Ion), and high on/off ratio (Ion/Ioff) must be realized. To improve these parameters, we first fabricated a high-k (∼30.5) yttrium-doped hafnium dioxide (Y:HfO2) film through a solution process to suppress Coulomb electron scattering, and to enhance the semiconductor-dielectric interface with an efficient metal–oxygen framework and a very smooth (root mean square = 0.29 nm) surface. Second, we induced Fermi level depinning by introducing a semimetal bismuth (Bi) contact with a low density of states (DOS) at the Fermi level to suppress the metal-induced gap state (MIGS). Through these two strategies, the SnS2 FET obtained high μFE (60.5 cm2V-1s−1), the SS theoretical limit of 60 mV/dec, negligible Schottky barrier height, high normalized on-current (IonL/W) of 90.6 μA, and high Ion/Ioff of 3 × 107, demonstrating that SnS2 can be re-evaluated as a potentially effective 2D channel material.

Взаимодействие электромагнитной Н-волны с наноструктурой "диэлектрик-полупроводник-диэлектрик" с учетом анизотропии зонной структуры полупроводника

The problem of electromagnetic H-wave interaction with a layered "insulator-semiconductor- insulator" nanostructure is solved. We assume that the semiconductor layer thickness can be comparable to or less than the charge carrier de Broglie wavelength. Charge carrier surface scattering is taken into account by the Soffer boundary conditions. The electromagnetic wave frequency is less than the plasma resonance frequency. The constant energy surface is an ellipsoid of revolution. Analytical expressions are obtained for the reflection, transmission and absorption coefficients. Calculations are performed for the limiting cases of a degenerate and nondegenerate electron gas. We analyze the dependences of the optical coefficients on dimensionless parameters: the semiconductor layer thickness, the electromagnetic wave frequency and incidence angle, the chemical potential, the ellipticity parameter, the insulating layer permittivities, and the semiconductor-insulator interface roughness parameters.

Assessment of interface trapped charge induced threshold voltage hysteresis effect in gate-all-around TFET

In this work, the impact of trapped charge carriers at the semiconductor-dielectric interface has been analyzed. The trapped charge causes the threshold voltage hysteresis effect during ramp up and ramps down of gate bias voltages. It has been shown that the trapped charge occupancy probability depends on the channel electric field and the bias ramp speed, which directly impacts the trapping and detrapping rate of the charge carrier. The simulation sanity has been verified by calibrating the transfer characteristics with the experimentally published data, where the impact on the threshold voltage has been examined by analyzing the impact of the electric field, trap occupation probabilities, band energy fluctuations, and generation and recombination rates. Our findings reveal that if a ramp timespan of 1 μsec is used for the device, then the threshold voltage hysteresis can be a serious reliability concern compared to 1 psec and 0.5 s ramp timespans of GAATFET devices.

All-Aerosol-Jet-Printed Carbon Nanotube Transistor with Cross-Linked Polymer Dielectrics.

The printability of reliable gate dielectrics and their influence on the stability of the device are some of the primary concerns regarding the practical application of printed transistors. Major ongoing research is focusing on the structural properties of dielectric materials and deposition parameters to reduce interface charge traps and hysteresis caused by the dielectric-semiconductor interface and dielectric bulk. This research focuses on improving the dielectric properties of a printed polymer material, cross-linked polyvinyl phenol (crPVP), by optimizing the cross-linking parameters as well as the aerosol jet printability. These improvements were then applied to the fabrication of completely printed carbon nanotube (CNT)-based thin-film transistors (TFT) to reduce the gate threshold voltage (Vth) and hysteresis in Vth during device operation. Finally, a fully aerosol-jet-printed CNT device was demonstrated using a 2:1 weight ratio of PVP with the cross-linker poly(melamine-co-formaldehyde) methylated (PMF) in crPVP as the dielectric material. This device shows significantly less hysteresis and can be operated at a gate threshold voltage as low as -4.8 V with an on/off ratio of more than 104.

Fine-Tuning the Performance of Ultraflexible Organic Complementary Circuits on a Single Substrate via a Nanoscale Interfacial Photochemical Reaction.

Flexible electronics has paved the way toward the development of next-generation wearable and implantable healthcare devices, including multimodal sensors. Integrating flexible circuits with transducers on a single substrate is desirable for processing vital signals. However, the trade-off between low power consumption and high operating speed is a major bottleneck. Organic thin-film transistors (OTFTs) are suitable for developing flexible circuits owing to their intrinsic flexibility and compatibility with the printing process. We used a photoreactive insulating polymer poly((±)endo,exo-bicyclo[2.2.1]hept-ene-2,3-dicarboxylic acid, diphenylester) (PNDPE) to modulate the power consumption and operating speed of ultraflexible organic circuits fabricated on a single substrate. The turn-on voltage (V on) of the p- and n-type OTFTs was controlled through a nanoscale interfacial photochemical reaction. The time-of-flight secondary ion mass spectrometry revealed the preferential occurrence of the PNDPE photochemical reaction in the vicinity of the semiconductor-dielectric interface. The power consumption and operating speed of the ultraflexible complementary inverters were tuned by a factor of 6 and 4, respectively. The minimum static power consumption was 30 ± 9 pW at transient and 4 ± 1 pW at standby. Furthermore, within the tuning range of the operating speed and at a supply voltage above 2.5 V, the minimum stage delay time was of the order of hundreds of microseconds. We demonstrated electromyogram measurements to emphasize the advantage of the nanoscale interfacial photochemical reaction. Our study suggests that a nanoscale interfacial photochemical reaction can be employed to develop imperceptible and wearable multimodal sensors with organic signal processing circuits that exhibit low power consumption.

Impact of Interface Traps in Floating-Gate Memory Based on Monolayer MoS

Two-dimensional materials (2DMs) have found potential applications in many areas of electronics, such as sensing, memory systems, optoelectronics, and power. Despite an intense experimental work, the literature is lacking of accurate modeling of nonvolatile memories (NVMs) based on 2DMs. In this work, using technology CAD simulations and model calibration with experiments, we show that the experimental program/erase characteristics of floating-gate (FG) memory devices based on monolayer molybdenum disulphide can be explained by considering bandgap trap states at the dielectric–semiconductor interface. The simulation model includes a classical approach based on drift-diffusion longitudinal channel transport and on nonlocal Wentzel–Kramers–Brillouin (WKB) tunneling for transversal transport (responsible of FG charging/discharging) and for tunneling at contacts. From hysteresis and pulse programming simulations on scaled devices, we find that the long-channel programming window is still maintained at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 100$ </tex-math></inline-formula> nm and that process improvements aimed at reducing the concentration of interface traps in the semiconducting bandgap could significantly optimize memory operation.

Physico-Chemical Origins of Electrical Characteristics and Instabilities in Solution-Processed ZnSnO Thin-Film Transistors

We investigate the physico-chemical origins that determine the transistor characteristics and stabilities in sol-gel processed zinc tin oxide (ZTO) thin-film transistors (TFTs). ZTO solutions with Sn/(Sn+Zn) molar ratios from 0.3 to 0.6 were synthesized to demonstrate the underlying mechanism of the electrical characteristics and bias-induced instabilities. As the Sn/(Sn+Zn) ratio of ZTO is increased, the threshold voltage of the ZTO TFTs negatively shifts owing to the gradual increase in the ratio of oxygen vacancies. The ZTO TFTs with an Sn/(Sn+Zn) ratio of 0.4 exhibit highest saturation mobility of 1.56 cm2/Vs lowest subthreshold swing and hysteresis of 0.44 V/dec and 0.29 V, respectively, due to the desirable atomic states of ZTO thin film. Furthermore, these also exhibit outstanding positive bias stability due to the low trap density at the semiconductor-dielectric interface. On the other hand, the negative bias stress-induced instability gradually increases as the proportion of tin increases because the negative bias stress instability originates from the ionization of oxygen vacancies. These results will contribute to the optimization of the composition ratio in rare-metal-free oxide semiconductors for next-generation low-cost electronics.

Hysteresis and turn-on voltage tailoring of indium gallium zinc oxide transistors by employing a sandwiched structure with indium oxide

• Transistor with ternary oxide semiconductor shows large hysteresis at low voltage. • Hysteresis can be addressed by improving semiconductor-dielectric interface. • Forming a sandwich structure with In 2 O 3 reduces hysteresis. • Turn-on voltage of transistors is controlled via the In 2 O 3 film thickness. Transparent electronics with low power consumption is an important area of research for the display industry. Operating voltages of transistors can be successfully reduced by employing gate dielectrics with high dielectric constants. However, interfacial trap sites between dielectric and semiconductor layers might cause hysteresis. Here, transistors were fabricated using amorphous indium gallium zinc oxide (a-IGZO, molar ratio of In:Ga:Zn 1:1:1), a transparent semiconductor with high electron mobility. When prepared on top of Al 2 O 3 gate dielectric, drain current was found to depend on the direction of the gate sweep. A stacked active layer was prepared with the a-IGZO being sandwiched between In 2 O 3 thin films to mitigate the hysteresis of the device. Moreover, it was found that by varying the In 2 O 3 layer thickness, the device fabrication can be optimized to improve the device-to-device reproducibility of the charge carrier mobility. Additionally, the turn-on voltage, a crucial parameter of transistors in binary logic circuits, improved significantly when using the optimized layer structure.