Semiconductor-insulator Interface Research Articles

The Criterion for Choosing an Insulator for Sili-con MOS Structures

Nowadays, MIS structures based on silicon dioxide films have become the most widely used. However, the desire to reduce the channel length and the nano-scaling in electronics showed, that SiO 2 can’t provide the specified MIS devices parameters and characteristics. This is due to the superfine insulator films problem. First of all, this can be solved by replacing SiO 2 with another insulator that meets certain requirements. Oxides of transition and rare-earth metals meets almost all of these requirements. However, the principle issue of insulator and semiconductor compatibility remains unsolved in terms of ensure theirs interface quality. Therefore, the researching purpose is to create a general approach to the selection of insulator which is an alternative to silicon dioxide. This insulator must provide a high quality of insulator-semiconductor interface. In MIS structures, the main indicator of semiconductor-insulator interface is its density of the electric charge. Low values of the charge density at the semiconductor-insulator interface are corresponds to high quality of the interface. This is due to the fact that low interface charge density has low affecting on threshold voltage and provide higher its stability. In the first approximation, the surface states density is identically equal to the incomplete bonds density at semiconductor-insulator interface. Therefore, this parameter is selected as the basis of the insulator choosing criterion for a particular semiconductor substrate. It is shown that the classical theory of crystalline lattice (site aspect) can't allow to obtain an analytical expression for the insulator choosing criterion for MIS structures. Therefore, a new form of description of a crystal lattice (intersite aspect) is proposed. Since the crystals differs not only by symmetry but also by the crystallographic orientation of their interface with the vacuum, then an infinite number of solutions about value of incomplete bonds density at the interface correspond to each pair of materials. For obtaining only the one solution by using insulator choosing criterion, a new characteristic parameter of the crystalline substance is introduced - the average bond length. To confirm the practical significance of the average bond length, the relationship between this parameter and electron work function is obtained. The experiment based on literary data of both electron work function and lattice constants was made. The experimental results proves both validity of the relationship and practical significance of the average bond length. On the basis of the intersite aspect and the average bond length, general insulator choosing criterion for MIS structures on certain semiconductor substrate was obtained. For replacement of silicon dioxide in silicon MIS devices, insulator was selected from suitable materials namely oxides of transition and rare-earth metals. The incomplete bonds density at the insulator-silicon interface was calculated for each of these materials. Analysis of the calculation results showed that, in accordance with the insulator choosing criterion, the most promising material is CeO 2 . The insulator choosing criterion for MIS structures on certain semiconductor substrate is proposed. Its allows, under other equal conditions, to choose the suitable insulator which will provide the least electric charge density at the insulator-semiconductor interface, in comparison with other pretenders. In case of a silicon substrate, such insulator is CeO 2 . A new characteristic parameter of a crystalline materials is introduced - the average bond length. The analytical expression, which get the relationship between this parameter and the electron work function, is obtained. The obtained results provide an opportunity to make choices insulator for MIS devices based on not only silicon substrates, but also any other semiconductor materials. The proposed insulator choosing criterion can serve as the basis for build new criteria. This ones can help in solving more complicated problems like choosing insulator for MIS devices based on semiconductor substrate with a certain crystallographic orientation. Bibl. 10, Fig. 9.

Geometric influence of cylindrical surface curvature on the electrostatics of thin film transistors

Thin film transistor (TFT) based integrated circuits on flexible substrates promise interesting approaches to human interface systems. TFTs have been fabricated on textured surfaces such as textiles, paper, artificially corrugated substrates and fibers. This can result in the metal–insulator–semiconductor stack being significantly distorted from a planar geometry to having high curvature. Although the direct deposition on textured surfaces does not result in mechanical stress (as opposed to that seen during bending, buckling, wrinkling), the geometry of high curvature can influence the characteristics of the TFT. Here we present a closed form analytical model describing the impact of high curvature on the electrical performance of the TFT. Models are obtained from the solution to the Poisson–Boltzmann equation in polar co-ordinates and are limited to cylindrical surface (zero Gaussian curvature) with the ratio of radius of curvature of the semiconductor–insulator interface, rsi, to insulator thickness, ti, ranging from to rsi/ti = 50. Models are verified using Technology Computer-Aided Design simulations performed using amorphous galium indium zinc oxide. Studies show that when the semiconductor–insulator interface is curved convex (normal vector into the gate) the interfacial free carrier concentration increases by 50% (for rsi/ti = 2) to 8.5% (for rsi/ti = 15) as compared to planar TFTs. On the other hand, when the curvature is concave, the free carrier concentration decreases by those percentages as compared to planar TFTs. Thus curvature can modulate TFT transconductance. Models show that the impact of curvature becomes negligible (<4% variation) for rsi/ti > 25. Techniques to generalize the results to periodic cylindrical surfaces and other semiconducting materials are discussed along with experimental verification. This work forms an analytical basis to understand the behavior of TFTs fabricated on textured substrates.

Photovoltage Reversal in Organic Optoelectronic Devices with Insulator-Semiconductor Interfaces.

Photoinduced space-charges in organic optoelectronic devices, which are usually caused by poor mobility and charge injection imbalance, always limit the device performance. Here we demonstrate that photoinduced space-charge layers, accumulated at organic semiconductor-insulator interfaces, can also play a role for photocurrent generation. Photocurrent transients from organic devices, with insulator-semiconductor interfaces, were systematically studied by using the double-layer model with an equivalent circuit. Results indicated that the electric fields in photoinduced space-charge layers can be utilized for charge generation and can even induce a photovoltage reversal. Such an operational process of light harvesting would be promising for photoelectric conversion in organic devices.

Gate modeling of metal–insulator–semiconductor devices based on ultra-thin atomic-layer deposited TiO2

Metal–insulator–semiconductor devices having different oxide thicknesses (10, 6, 4 and 2 nm) were fabricated using atomic-layer deposited ultra-thin amorphous TiO2 as gate dielectric. From Ig–Vg measurements it was determined that the main conduction mechanism is Schottky emission for all thicknesses and even after passivation of the semiconductor–insulator interface using SiOx. Furthermore, the Schottky barrier height (ΦB) increases when the oxide thickness decreases; this was further corroborated using semi empirical models and SILVACO simulations having excellent agreement. From this analysis, important physical parameters like barrier height (ΦB), effective mass (m*) and optical dielectric constant (er) were extracted, and could be used to effectively understand the performance and reliability of these devices. From the extraction of physical parameters associated to the conduction mechanism, a correlation between materials’ properties with device performance could be obtained (higher barrier height (ΦB) would result in a decrease in leakage current). Also, the high reproducibility enables enhanced performance and therefore, better reliability predictions for electron devices based on these oxides.

Synergistic Gating of Electro-Iono-Photoactive 2D Chalcogenide Neuristors: Coexistence of Hebbian and Homeostatic Synaptic Metaplasticity.

Emulation of brain-like signal processing with thin-film devices can lay the foundation for building artificially intelligent learning circuitry in future. Encompassing higher functionalities into single artificial neural elements will allow the development of robust neuromorphic circuitry emulating biological adaptation mechanisms with drastically lesser neural elements, mitigating strict process challenges and high circuit density requirements necessary to match the computational complexity of the human brain. Here, 2D transition metal di-chalcogenide (MoS2 ) neuristors are designed to mimic intracellular ion endocytosis-exocytosis dynamics/neurotransmitter-release in chemical synapses using three approaches: (i) electronic-mode: a defect modulation approach where the traps at the semiconductor-dielectric interface are perturbed; (ii) ionotronic-mode: where electronic responses are modulated via ionic gating; and (iii) photoactive-mode: harnessing persistent photoconductivity or trap-assisted slow recombination mechanisms. Exploiting a novel multigated architecture incorporating electrical and optical biases, this incarnation not only addresses different charge-trapping probabilities to finely modulate the synaptic weights, but also amalgamates neuromodulation schemes to achieve "plasticity of plasticity-metaplasticity" via dynamic control of Hebbian spike-time dependent plasticity and homeostatic regulation. Coexistence of such multiple forms of synaptic plasticity increases the efficacy of memory storage and processing capacity of artificial neuristors, enabling design of highly efficient novel neural architectures.

Detection of the Interface-Trap Charge Density and Lateral Nonuniformity of Through-Silicon Vias

Through-silicon via (TSV) technology has emerged as a key component of 3-D integrated circuits. As the integration density in a package increases, the nonlinear metal–oxide–semiconductor (MOS) capacitance in TSVs has a greater effect on the electrical performance of the devices. Imperfections due to the deposition of a dielectric layer are important factors which can change the characteristics of the MOS capacitance. This letter presents a method by which to detect the interface-trap charge density $\text{D}_{\mathbf {it}}$ and lateral nonuniformity (LNU) of imperfections in TSVs. The results of an analysis of a measured sample define $\text{D}_{\mathbf {it}}$ and LNU at the dielectric–semiconductor interface and demonstrate that the presence of LNU can be established by a negative $\text{D}_{\mathbf {it}}$ .

Graphene-insulator-semiconductor capacitors as superior test structures for photoelectric determination of semiconductor devices band diagrams

We report on the advantages of using Graphene-Insulator-Semiconductor (GIS) instead of Metal-Insulator-Semiconductor (MIS) structures in reliable and precise photoelectric determination of the band alignment at the semiconductor-insulator interface and of the insulator band gap determination. Due to the high transparency to light of the graphene gate in GIS structures large photocurrents due to emission of both electrons and holes from the substrate and negligible photocurrents due to emission of carriers from the gate can be obtained, which allows reliable determination of barrier heights for both electrons, Ee and holes, Eh from the semiconductor substrate. Knowing the values of both Ee and Eh allows direct determination of the insulator band gap EG(I). Photoelectric measurements were made of a series of Graphene-SiO2-Si structures and an example is shown of the results obtained in sequential measurements of the same structure giving the following barrier height values: Ee = 4.34 ± 0.01 eV and Eh = 4.70 ± 0.03 eV. Based on this result and results obtained for other structures in the series we conservatively estimate the maximum uncertainty of both barrier heights estimations at ± 0.05 eV. This sets the SiO2 band gap estimation at EG(I) = 7.92 ± 0.1 eV. It is shown that widely different SiO2 band gap values were found by research groups using various determination methods. We hypothesize that these differences are due to different sensitivities of measurement methods used to the existence of the SiO2 valence band tail.

Influence of quantizing magnetic field and Rashba effect on indium arsenide metal-oxide-semiconductor structure accumulation capacitance

The accumulation capacitance oscillations behavior in the n-InAs metal-oxide-semiconductor structures with different densities of the built-in charge (Dbc) and the interface traps (Dit) at temperature 4.2 K in the magnetic field (B) 2–10 T, directed perpendicular to the semiconductor-dielectric interface, is studied. A decrease in the oscillation frequency and an increase in the capacitance oscillation amplitude are observed with the increase in B. At the same time, for a certain surface accumulation band bending, the influence of the Rashba effect, which is expressed in the oscillations decay and breakdown, is traced. The experimental capacitance-voltage curves are in a good agreement with the numeric simulation results of the self-consistent solution of Schrödinger and Poisson equations in the magnetic field, taking into account the quantization, nonparabolicity of dispersion law, and Fermi-Dirac electron statistics, with the allowance for the Rashba effect. The Landau quantum level broadening in a two-dimensional electron gas (Lorentzian-shaped density of states), due to the electron scattering mechanism, linearly depends on the magnetic field. The correlation between the interface electronic properties and the characteristic scattering times was established.

Reduction of Charge Traps and Stability Enhancement in Solution-Processed Organic Field-Effect Transistors Based on a Blended n-Type Semiconductor.

Solution-processed n-type organic field-effect transistors (OFETs) are essential elements for developing large-area, low-cost, and all organic logic/complementary circuits. Nonetheless, the development of air-stable n-type organic semiconductors (OSCs) lags behind their p-type counterparts. The trapping of electrons at the semiconductor-dielectric interface leads to a lower performance and operational stability. Herein, we report printed small-molecule n-type OFETs based on a blend with a binder polymer, which enhances the device stability due to the improvement of the semiconductor-dielectric interface quality and a self-encapsulation. Both combined effects prevent the fast deterioration of the OSC. Additionally, a complementary metal-oxide semiconductor-like inverter is fabricated depositing p-type and n-type OSCs simultaneously.

Improvement in electrostatic characteristics of doped TFETs by hole layer formation

We present a distinct approach to enhance the performance of physically doped tunnel field-effect transistors (TFETs) based on creation of a layer of positive charge at the semiconductor–insulator interface in the source region. Formation of such a hole layer resolves the issue related to material solubility and improves direct-current (DC) as well as high-frequency figures of merit. To implement this approach, a typical $$P^{+}$$ -I- $$N^{+}$$ -type physically doped TFET structure is considered. Furthermore, a metal electrode with workfunction of 4.53 eV is placed over the heavily doped $$P^{+}$$ source region with a negative supply voltage. The negative voltage at the source electrode attracts holes from the source region and creates a hole layer just below the semiconductor–insulator interface. This phenomenon makes the source–channel junction abrupt and reduces the tunneling barrier width, resulting in higher tunneling generation rate of charge carriers at the source–channel junction. Thus, the proposed device shows 100-fold increased ON-state current and a threshold voltage reduction of 300 mV. Analog/radiofrequency (RF) parameters are also greatly improved compared with the conventional device. Furthermore, optimization of the spacer length ( $$L_\mathrm{SG}$$ ), i.e., the gap between the source and gate electrode, and application of a negative voltage ( $$-V_\mathrm{SE}$$ ) at the source electrode (SE), were applied to achieve the optimum performance. Moreover, device linearity was also analyzed in a comparative manner.

Insulator-semiconductor interface fixed charges in AlGaN/GaN metal-insulator-semiconductor devices with Al2O3 or AlTiO gate dielectrics

We have investigated insulator-semiconductor interface fixed charges in AlGaN/GaN metal-insulator-semiconductor (MIS) devices with Al2O3 or AlTiO (an alloy of Al2O3 and TiO2) gate dielectrics obtained by atomic layer deposition on AlGaN. Analyzing insulator-thickness dependences of threshold voltages for the MIS devices, we evaluated positive interface fixed charges, whose density at the AlTiO/AlGaN interface is significantly lower than that at the Al2O3/AlGaN interface. This and a higher dielectric constant of AlTiO lead to rather shallower threshold voltages for the AlTiO gate dielectric than for Al2O3. The lower interface fixed charge density also leads to the fact that the two-dimensional electron concentration is a decreasing function of the insulator thickness for AlTiO, whereas being an increasing function for Al2O3. Moreover, we discuss the relationship between the interface fixed charges and interface states. From the conductance method, it is shown that the interface state densities are very similar at the Al2O3/AlGaN and AlTiO/AlGaN interfaces. Therefore, we consider that the lower AlTiO/AlGaN interface fixed charge density is not owing to electrons trapped at deep interface states compensating the positive fixed charges and can be attributed to a lower density of oxygen-related interface donors.

Conservation of quantum efficiency in quantum well intermixing by stress engineering with dielectric bilayers

In semiconductor lasers, quantum well intermixing (QWI) with high selectivity using dielectrics often results in lower quantum efficiency. In this paper, we report on an investigation regarding the effect of thermally induced dielectric stress on the quantum efficiency of quantum well structures in impurity-free vacancy disordering (IFVD) process using photoluminescence and device characterization in conjunction with microscopy. SiO2 and SixO2/SrF2 (versus SrF2) films were employed for the enhancement and suppression of QWI, respectively. Large intermixing selectivity of 75 nm (125 meV), consistent with the theoretical modeling results, with negligible effect on the suppression region characteristics, was obtained. SixO2 layer compensates for the large thermal expansion coefficient mismatch of SrF2 with the semiconductor and mitigates the detrimental effects of SrF2 without sacrificing its QWI benefits. The bilayer dielectric approach dramatically improved the dielectric–semiconductor interface quality. Fabricated high power semiconductor lasers demonstrated high quantum efficiency in the lasing region using the bilayer dielectric film during the intermixing process. Our results reveal that stress engineering in IFVD is essential and the thermal stress can be controlled by engineering the dielectric strain opening new perspectives for QWI of photonic devices.

Counteracting Threshold-Voltage Drift in Ion-Selective Field Effect Transistors (ISFETs) Using Threshold-Setting Ion Implantation

Ion-selective field effect transistors (ISFETs) exhibit instability, commonly known as drift, in the form of a slow, monotonic, temporal increase in the threshold voltage of the device. A method for counteracting instability inspired by a physical model for threshold voltage drift in pH-sensitive ISFETs is presented. This method involves adjusting the charge density at the insulator-semiconductor interface using threshold-setting ion implantation such that the net charge induced in the semiconductor at the operating point of the device is minimized. The proposed method is analytically validated based on characterization and modeling of drift in an Al2O3-gate pH-sensitive ISFET. Counteraction of ISFET drift by ion implantation is also demonstrated using TCAD simulations. The optimum donor-type implant dose of $3.25 \times 10^{11}$ cm−2 determined based on ATLAS simulations is in good agreement with the corresponding dose of $6.58 \times 10^{11}$ cm−2 obtained analytically.

Measuring the lateral charge-carrier mobility in metal-insulator-semiconductor capacitors via Kelvin-probe.

We report a Kelvin-probe method to investigate the lateral charge-transport properties of semiconductors, most notably the charge-carrier mobility. The method is based on successive charging and discharging of a pre-biased metal-insulator-semiconductor stack by an alternating voltage applied to one edge of a laterally confined semiconductor layer. The charge carriers spreading along the insulator-semiconductor interface are directly measured by a Kelvin-probe, following the time evolution of the surface potential. A model is presented, describing the device response for arbitrary applied biases allowing the extraction of the lateral charge-carrier mobility from experimentally measured surface potentials. The method is tested using the organic semiconductor poly(3-hexylthiophene), and the extracted mobilities are validated through current voltage measurements on respective field-effect transistors. Our widely applicable approach enables robust measurements of the lateral charge-carrier mobility in semiconductors with weak impact from the utilized contact materials.

Новый механизм реализации омических контактов

AbstractAnalysis of the contact-barrier height taking into account the distribution of surface states along coordinate x perpendicular to the insulator–semiconductor interface is performed for metal–semiconductor contacts with a dielectric gap. It is shown that taking into account the spatial dependence of the density of surface states at rather high semiconductor doping levels leads to a substantial decrease in the barrier height, which promotes the realization of ohmic contacts. It is established that the smaller the metal–semiconductor contact potential difference ϕ_ ms is, the stronger the effect of barrier-height lowering. If ϕ_ ms is negative, this effect can lead to potential sign reversal, i.e., to the realization of an enrichment layer in the space-charge region of the semiconductor even at a high density of surface states. This in turn promotes the manifestation of an anomalous dependence of the contact resistivity on temperature; the resistivity increases with an increase in temperature.

On a New Mechanism for the Realization of Ohmic Contacts

Analysis of the contact-barrier height taking into account the distribution of surface states along coordinate x perpendicular to the insulator–semiconductor interface is performed for metal–semiconductor contacts with a dielectric gap. It is shown that taking into account the spatial dependence of the density of surface states at rather high semiconductor doping levels leads to a substantial decrease in the barrier height, which promotes the realization of ohmic contacts. It is established that the smaller the metal–semiconductor contact potential difference ϕ ms is, the stronger the effect of barrier-height lowering. If ϕ ms is negative, this effect can lead to potential sign reversal, i.e., to the realization of an enrichment layer in the space-charge region of the semiconductor even at a high density of surface states. This in turn promotes the manifestation of an anomalous dependence of the contact resistivity on temperature; the resistivity increases with an increase in temperature.

Photon induced non-linear quantized double layer charging in quaternary semiconducting quantum dots

Room temperature quantized double layer charging was observed in 2 nm Cu2ZnSnS4 (CZTS) quantum dots. In addition to this we observed a distinct non-linearity in the quantized double layer charging arising from UV light modulation of double layer. UV light irradiation resulted in a 26% increase in the integral capacitance at the semiconductor-dielectric (CZTS-oleylamine) interface of the quantum dot without any change in its core size suggesting that the cause be photocapacitive. The increasing charge separation at the semiconductor-dielectric interface due to highly stable and mobile photogenerated carriers cause larger electrostatic forces between the quantum dot and electrolyte leading to an enhanced double layer. This idea was supported by a decrease in the differential capacitance possible due to an enhanced double layer. Furthermore the UV illumination enhanced double layer gives us an AC excitation dependent differential double layer capacitance which confirms that the charging process is non-linear. This ultimately illustrates the utility of a colloidal quantum dot-electrolyte interface as a non-linear photocapacitor.

Modulating Thin Film Transistor Characteristics by Texturing the Gate Metal

The development of reliable, high performance integrated circuits based on thin film transistors (TFTs) is of interest for the development of flexible electronic circuits. In this work we illustrate the modulation of TFT transconductance via the texturing of the gate metal created by the addition of a conductive pattern on top of a planar gate. Texturing results in the semiconductor-insulator interface acquiring a non-planar geometry with local variations in the radius of curvature. This influences various TFT parameters such as the subthreshold slope, gate voltage at the onset of conduction, contact resistance and gate capacitance. Specific studies are performed on textures based on periodic striations oriented along different directions. Textured TFTs showed upto ±40% variation in transconductance depending on the texture orientation as compared to conventional planar gate TFTs. Analytical models are developed and compared with experiments. Gain boosting in common source amplifiers based on textured TFTs as compared to conventional TFTs is demonstrated.

Threshold voltage peculiarities and bias temperature instabilities of SiC MOSFETs

Silicon carbide (SiC) based metal-oxide semiconductor-field-effect-transistors (MOSFETs) are increasingly entering the high power device market. Besides all the well-known benefits which come along with these new generations of switches, the nature of the wide bandgap material and the different properties of the semiconductor-dielectric interface involve some natural peculiarities in threshold voltage variation and bias-temperature-instability (BTI) which differ from comparable silicon (Si) MOSFET counterparts and which need to be understood and assessed. The target of this paper is to highlight such differences, explain their relation to the semiconductor material, challenge their relevance for the application and define their consequences with regard to datasheet specifications. Most of the new effects can be understood by means of simple physical models and do not compromise the reliability of the device. However, it turns out that the standard test procedures typically used to characterize threshold voltage and threshold voltage drifts for Si devices need to be adapted for SiC MOSFETs. A new measure-stress-measure procedure for BTI evaluation of SiC MOSFETs is proposed which allows distinguishing between reversible threshold voltage hysteresis and more permanent threshold voltage drift (BTI). The measurement pattern is then used to assess the VTH stability of recently launched SiC MOSFET parts. The tested devices differ considerably in BTI drift amplitude and drift variation. The differences are attributed to variations in device processing and device design.

Fast and slow traps in Al2O3/(GaN)/AlGaN/GaN heterostructures studied by conductance technique

Influence of interface traps at Al2O3/(GaN)/AlGaN interface at low and high frequency on equivalent parallel conductance of Al2O3/(GaN)/AlGaN/GaN heterostructure capacitor was studied. By the conductance measurements two types of traps were identified in the measured structure. The traps differ in time constants by more than one order in magnitude. Fast traps with low time constants have narrow energy distribution and are probably located in the semiconductor energy gap close to the insulator semiconductor interface. Slow traps have wider distribution and are assumed to be directly at the insulator semiconductor interface. The presence of the fast traps which are able to respond to external ac signal is given into connection with the recently published increase of the structure capacitance in the plateau region with decreasing frequency.