Detection of the Interface-Trap Charge Density and Lateral Nonuniformity of Through-Silicon Vias

Abstract

Through-silicon via (TSV) technology has emerged as a key component of 3-D integrated circuits. As the integration density in a package increases, the nonlinear metal–oxide–semiconductor (MOS) capacitance in TSVs has a greater effect on the electrical performance of the devices. Imperfections due to the deposition of a dielectric layer are important factors which can change the characteristics of the MOS capacitance. This letter presents a method by which to detect the interface-trap charge density $\text{D}_{\mathbf {it}}$ and lateral nonuniformity (LNU) of imperfections in TSVs. The results of an analysis of a measured sample define $\text{D}_{\mathbf {it}}$ and LNU at the dielectric–semiconductor interface and demonstrate that the presence of LNU can be established by a negative $\text{D}_{\mathbf {it}}$ .