A novel circuit model for multiple Through Silicon Vias (TSVs) in 3D IC

Abstract

Electrical modeling of Through Silicon Vias (TSVs) is very important for three dimensional (3D) system design and analysis. It has attracted much research attention in recent years. Most of the previous research focuses on fitting circuit parameters to the frequency response obtained from measurements or full-wave discretization based electromagnetic simulations. The extension of these methods to multiple TSVs can be challenging because of the significant increase in computational cost. In this paper, we proposed a novel circuit model for multiple TSVs. Since frequent switching of high speed signals can dynamically bias TSV metal insulator semiconductor (MIS) interface and allocate TSV MIS into accumulation or depletion regions, the TSV capacitance is nonlinear and dependent on the biasing of the TSVs. An analytical expression for capacitance is introduced and a new circuit model is proposed accordingly. The circuit model accurately captures all the parasitic elements of various TSVs arrangements and accounts for wide frequency range, high frequency skin effect, eddy currents in substrate, and metal oxide semiconductor (MOS) effect.