Modeling the effect of charges in the back side passivation layer on through silicon via (TSV) capacitance after wafer thinning

Abstract

Evaluating the importance of electromagnetic (EM) coupling from through silicon vias (TSVs) has become crucial to the design of three-dimensional integrated circuits (3D-ICs). One of the most important parasitic contributions to signal propagation in 3D-ICs is the TSV capacitance. It is both frequency and bias dependent since a TSV is a metal-oxide-semiconductor (MOS) structure. In this work, anomalous TSV capacitance behavior after wafer thinning is reported and investigated by combining measurements and finite element (FEM) semiconductor simulations. Excellent agreement between models and experimental data confirms the origin of the anomalous TSV capacitance behavior: the presence of fixed charges in the back side (BS) passivation layer of the TSV after wafer thinning. In addition, a BS inversion layer can act as a conductive channel between neighboring vias, increasing the capacitive coupling between TSVs. Calibrated equivalent circuit models of the TSV in contact with a BS inversion layer are proposed for the first time in the context of 3D integration and validated.