Device Wafer Research Articles

Wafer-Level Vacuum Packaging Enabled by Plastic Deformation and Low-Temperature Welding of Copper Sealing Rings With a Small Footprint

Wafer-level vacuum packaging is vital in the fabrication of many microelectromechanical systems (MEMS) devices and enables significant cost reduction in high-volume MEMS production. In this paper, we propose a low-temperature wafer-level vacuum packaging method based on plastic deformation and low-temperature welding of copper sealing rings with a small footprint. A device wafer with copper ring structures and a cap wafer with corresponding metalized grooves are placed inside a vacuum chamber and pressed together at a temperature of 250 °C, resulting in low-temperature welding of the copper, and thus, hermetic sealing of the cavities enclosed by the sealing rings. The vacuum pressure inside the fabricated cavities 146 days after bonding was measured using residual gas analysis to be as low as $2.6\times 10^{-2}$ mbar. Based on this value, the leak rate is calculated to be smaller than $ {3.6}\times {10}^{-16}$ mbarL/s using the most conservative assumptions, demonstrating the excellent hermeticity of the seals. Shear testing was used to demonstrate that the seals are mechanically stable with over 90 MPa in shear strength for $5.2~\mu \text{m}$ -high Cu sealing rings with widths down to $8~\mu \text{m}$ . The reported method is potentially compatible with complementary metal-oxide-semiconductor (CMOS) substrates and may be applied to vacuum packaging of 3-D heterogeneously integrated MEMS on state-of-the-art CMOS substrates. [2016-0252]

Laser Debonding for 2.5D, 3D and Emerging Advanced Packaging Solutions

In recent years temporary bonding has evolved to a widely used process technology as it is an enabling process for many products relyinnovel solutions are typically assessed on two key criteria which are a broad process window and cost effectiveness. Thus in this paper these criteria will be discussed in more detail for the case of UV laser debonding with respect to wafer level packaging. By temporary bonding the thin or to be thinned device wafer is bonded to a carrier wafer by an adhesive interlayer to provide sufficient mechanical support which is crucial for many downstream processes. In the past several different technologies have been studied and implemented. A major differentiation factor between the offered solutions is the debonding method, including separation processes at room or elevated temperatures. Nowadays a particular focus is on UV laser debonding as it offers several advantages, as the debonding process can be performed at room temperature with fast process times and force free separation. Furthermore crosslinking adhesive materials with high temperature stability can be used. This can be achieved due to the high intensity UV light provided by an excimer laser system which is absorbed by the polymer close to the carrier surface and breaks the chemical bonds. The low debonding temperature in combination with high temperature stability of the adhesives leads to a broad process window for the temporary bonded stack. In addition transparent adhesive materials can be used in combination with the glass carrier to support better visibility of alignment marks within the bond interface. However, for industrial requirement besides the technical advantages the most critical parameters are ease of implementation, throughput and costs. In this paper we will review integration principles for advanced packaging as well as new devices that utilize temporary bonding. Special focus will also be put on upcoming demands for future device concepts. A short discussion will discuss temporary bonding methods and materials, benefits and drawbacks of each one. In the following laser debonding will be discussed as a focus topic for next generation packaging process technology. Laser debonding is already being applied in volume for couple of technologies, focussing on different wavelengths. We will focus on a newly developed technology, using UV solid state laser technology. Here, we will discuss all relevant process parameter, critical process steps along with reliability of different laser debonding material systems.

Si-gold-glass hybrid wafer bond for 3D-MEMS and wafer level packaging

We report a relatively low temperature (<400 °C) hybrid wafer bonding process that results in the simultaneous anodic and eutectic bonding in different predetermined regions of the wafer. This hybrid bonding process has potential applications in CMOS-MEMS device integration and wafer level packaging. We demonstrate the process by realizing a simple MEMS cantilever beam and a complex MEMS gyroscope structure. These structures are characterized for ohmic contact and electromechanical response to verify the electrical interconnect and the mechanical strength of the structure at the bond interface.

Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding.

Device encapsulation and packaging often constitutes a substantial part of the fabrication cost of micro electro-mechanical systems (MEMS) transducers and imaging sensor devices. In this paper, we propose a simple and cost-effective wafer-level capping method that utilizes a limited number of highly standardized process steps as well as low-cost materials. The proposed capping process is based on low-temperature adhesive wafer bonding, which ensures full complementary metal-oxide-semiconductor (CMOS) compatibility. All necessary fabrication steps for the wafer bonding, such as cavity formation and deposition of the adhesive, are performed on the capping substrate. The polymer adhesive is deposited by spray-coating on the capping wafer containing the cavities. Thus, no lithographic patterning of the polymer adhesive is needed, and material waste is minimized. Furthermore, this process does not require any additional fabrication steps on the device wafer, which lowers the process complexity and fabrication costs. We demonstrate the proposed capping method by packaging two different MEMS devices. The two MEMS devices include a vibration sensor and an acceleration switch, which employ two different electrical interconnection schemes. The experimental results show wafer-level capping with excellent bond quality due to the re-flow behavior of the polymer adhesive. No impediment to the functionality of the MEMS devices was observed, which indicates that the encapsulation does not introduce significant tensile nor compressive stresses. Thus, we present a highly versatile, robust, and cost-efficient capping method for components such as MEMS and imaging sensors.

Behavior of copper contamination on backside damage for ultra-thin silicon three dimensional stacking structure

Bumpless interconnects and ultra-thinning of 300mm wafers for three-dimensional stacking technology have been studied. In our previous work, thinning effects using device wafers <10μm thick were reported. No degradation occurred in the retention time even in a 4-μm-thick DRAM wafer. In this study, the behavior of Cu contamination on a <3-μm-thick DRAM wafer was investigated. The wafer was thinned down by coarse (#320 grit size) grinding and fine (#2000 grit size) grinding. This thinning condition had 200-nm-thick ground damage remaining for the gettering effect. The DRAM wafer was intentionally contaminated with Cu on the damaged layer, and 250°C-60min of heating was carried out during adhesive bonding and de-bonding. Degradation in the device characteristics was found. However, the analytical results indicated that the Cu did not diffuse into the thin Si. Thus, a Cu contaminated blanket wafers having a damaged layer were prepared and annealed until 1000°C-30min. Secondary ion mass spectroscopy, transmission electron microscopy and positron annihilation spectroscopy were evaluated. The Cu was trapped in the vacancy-type defects of the 200nm damaged layer until a 700°C anneal. After an 800°C anneal, the Cu was eliminated on the damaged surface because of the Si recrystallization. The gettering ability of the damaged layer is suitable for 3D multi-level stacking regarding thermal stability.

Temporary Wafer Bonding Materials with Mechanical and Laser Debonding Technologies for Semiconductor Device Processing

Abstract Advanced wafer-level packaging (WLP) techniques, mainly driven by high performance applications in memory and mobile market, have been adopted for large-scale manufacturing in recent years. Temporary wafer bonding and debonding technology has been widely studied and developed over the last decade for use in various WLP technologies, such as package-on-package (PoP), fan-out integration, and 2.5-D and 3-D integration using through-silicon-via (TSV). Temporary bonding technology enables handling of thinned substrates (&amp;lt;100 μm), which can no longer self-support during backside processing and packaging. Moreover, some applications require the temporary bonding materials to withstand temperatures up to 250°C in high-vacuum conditions, and even up to 350°C or higher during the dopant activation step required for manufacturing power devices. Therefore, a simple yet effective temporary bonding process and material that can survive all the backside processes is highly desired. In this study, a series of formulations based on polar thermoplastics were developed for temporary wafer bonding applications. These materials target high temperature survivability and improved adhesion to prevent the premature delamination during downstream wafer processing. All of these materials provide high thermal stability up to 250°C or higher, and are able to be bonded to carrier wafers treated with release layers, which can be selectively debonded by either mechanical or laser release after backside processing. The material left on device wafer after debonding can be easily cleaned using common industrial solvents. Wafers bonded with these materials demonstrate lower overall stack total thickness variation (TTV &amp;lt; 5 μm) after grinding and have successfully passed a 200°C PECVD process without any delamination during grinding and PECVD processes.

Package Thickness - Ultrathin WLFO (Wafer-Level Fan-Out)

Abstract NANIUM's Fan-Out Wafer-Level Packaging technology WLFO (Wafer-Level Fan-Out) is based on embedded Wafer-Level Ball Grid Array technology eWLB of Infineon Technologies [1]. Since it′s invention almost 10 years ago, it became the leading technology for Fan-Out Wafer-Level packages. The WLFO technology is based upon the reconstitution of KGD (known good die) from incoming device wafer, independent of wafer diameter and material, to recon wafer format of active semiconductor dies or other active/passive components separated by mold compound applied through compression molding on a temporary mold carrier. The resulting recon wafer can be processed in standard wafer processing equipment. One of the challenges for the future of semiconductor packaging is reduction of the board level volume real estate occupied by each component. With the drive towards lower profile end user devices incorporating large display area and battery life the three dimensional space available for semiconductor packages is diminishing. It is well known that WLFO single die packaging but even more significant system integration enables the shrinkage of the XY footprint of the package through flexible very dense heterogeneous system-in-package integration [2]. But one of the disruptive advantages of the substrate-less WLFO technology is to also permit significant reduction of the overall package height (Z). A total package height for a BGA package including solder balls &amp;lt;500um and for a LGA package with solder land pads only &amp;lt;300um is achievable today, and further development towards even thinner packages is on the way.

Технология лазерной резки кремниевых пластин на кристаллы органических светоизлучающих диодов

The article deals with the matter of crystal quality in the production of microdisplays based on organic light-emitting diodes (OLEDs) after separation. This work aimed at increasing the product yield in cutting a silicon device wafer into chips by a method based on laser controlled thermocracking (LCT). This paper considers the laser processes performed on a laser system RT-350 assessed by the heating effect on OLED structures. Data for rating the merit of the surfaces of chips after the laser controlled thermocracking and dicing, namely, the availability and size of the chipping, as well as surface roughness are presented and compared. The authors substantiated the possibility of increasing efficiency and quality in the process of cutting silicon device wafers with a thickness of 725 microns into OLEDs for microdisplays production.

(Invited) Pattern and Emissivity Insensitive Dopant Activation and Silicide Contact Formation Annealing in a Hot Wall Rapid Thermal Annealing System

Local temperature non-uniformity during rapid thermal annealing (RTA) is an important contributor to within-die process variations which cause significant problems for advanced complimentary metal-oxide-semiconductor (CMOS) device manufacturing. RTA-induced variations strongly depend on circuit layout patterns and optical properties of exposed materials on the surface of the Si wafers. To reduce the “pattern effect”, a hot wall (furnace-based) RTA approach has been proposed and compared with a conventional cold wall (lamp-based) RTA approach in device manufacturing. Nickel and cobalt silicide formations on implanted single crystalline Si in the source/drain region, and implanted poly-Si word lines of memory devices were studied over wide ranges of RTA temperature and time using a hot wall RTA system, which uses mainly natural convection and conduction through ambient gas. Differences between cold wall (radiant) and hot wall (non-radiant) heating on the silicide formation and dopant profiles are compared. The hot wall RTA resulted in superior process uniformity and repeatability regardless of pattern size and emissivity differences on device wafers. Local metal film thickness variations and its interaction with local temperature non-uniformity during RTA are identified as major contributors for the silicidation process variations such as non-uniformity and non-repeatability.

Dielectric Coating Thermal Stabilization During GaAs-Based Laser Fabrication for Improved Device Yield

The quality and yield of GaAs-based ridge waveguide devices fabricated at MIT Lincoln Laboratory were negatively impacted by the random lot-to-lot appearance of blisters in the front-side contact metal. The blisters signaled compromised adhesion between the front-side contact metal, underlying SiO2 dielectric coating, and semiconductor surface. A thermal-anneal procedure developed for the fabrication of GaAs slab coupled optical waveguide (SCOW) ridge waveguide devices stabilizes the SiO2 dielectric coating by means of outgassing and stress reduction. This process eliminates a primary source of adhesion loss, as well as blister generation, and thereby significantly improves device yield. Stoney’s equation was used to analyze stress-induced bow in device wafers fabricated using this stabilization procedure. This analysis suggests that changes in wafer bow contribute to the incidence of metal blisters in SCOW devices.

Critical Process Parameters And Failure Analysis For Temporary Bonded Wafer Stacks

Temporary bonding is a ley process for almost any 3D integration scheme. It offers not only more stability during the thinning process but also allows handling for backside processing of thin wafers like interposers during subsequent process steps [1–2]. Although the temporary bonding technology is already used in high volume manufacturing and has proven high yield process, nevertheless, some limitation appears for some specific applications [3-4-5]. One critical failure origin is delamination, which can lead to wafer breakage and therefore yield loss. This separation of the device wafer and the carrier wafer typically occurs when the temporary bonded wafer stack (device wafer, carrier wafer and temporary bonding adhesive in between) experiences further processing done under high temperature and low vacuum like PECVD deposition. Further insight into processing parameters and a better understanding of the key contributing factors as well as its dependencies help to prevent this failure. To investigate the root cause of the delamination, thermoplastic materials, which are widely used for temporary bonding and debonding applications have been used as temporary bonding adhesives in this work. Different process parameters were investigated individually but also in combination to find the origin of the delamination. These parameters include post thinning annealing temperature, which was varied up to 370C, vacuum level, thermal gradient, bow and warp and intrinsic stress of the thin device wafer. After evaluation of the main parameters affecting the delamination appearance, two extreme cases were experimented in order to check the hypothesis. The first one exhibits delaminations even using a very soft processing conditions for a temporary bonding integration and the second case is able to withstand extreme processing conditions like high temperature up to 370C under vacuum of about 1mbar without delamination appearance. In addition, during this work, the mechanical coupling existing between the carrier and the device wafer thanks to the adhesive has been investigated. Here, a thermoplastic material was used in a temporary bonded structures using wafers with different coefficients of thermal expansion (CTE). During thermal treatment, this CTE difference induce important internal stress bow of the wafer stack. The temperature dependence of the mechanical coupling is monitored during the annealing. A mechanical decoupling between the two wafers occurs when above the polymer glass transition temperature. As a result, the rheology of the thermoplastic layer is found as a contributor to the delamination mechanism. Critical combinations of process parameters in temporary bonding process are then clearly identified and will be presented in this work.

Laser Direct Patterning of Dry Etch BCB Adhesive Layers for Low Temperature Permanent Wafer-to-Wafer Bonding

To enable advanced wafer level packaging approaches for devices like MEMS, image sensors or optical elements, wafer-to-wafer bonding processes using structured low temperature curable adhesives are required. A lot of Benzocyclobutene (BCB)-based wafer bonding works have been reported in the past showing a broad range of applications and good performance, but also some limitations such as long bond cycles and high cure temperature of 250 °C. In 2013 new process concepts were demonstrated [1], showing that wafer bond cycle time can be reduced to less than 10 min and a post bond batch cure at temperatures below 200 °C can be used to significantly shrink the overall cost of a BCB-based adhesive wafer bonding process. In order to create a patterned BCB bond layer, photo structuring of CYCLOTENE ® 4000 Resin is one solution. However, due to the decreased flow capability of that material after exposure, high bond forces and extended bonding times during wafer bonding as well as nearly flat surfaces with low topography are required for void-free bonding. To overcome these limitations, an increased material flow capability during wafer bonding is required. In this context non-photo sensitive CYCLOTENE ® 3000 Resin is suitable, since it has excellent flow capability in non-cured state. However, non-cured CYCLOTENE ® 3000 Resin cannot be structured with standard dry etching processes using a photo resist layer as mask. In order to enable patterned adhesive bonding based on CYCLOTENE ® 3000 Resin, alternative structuring methods have to be evaluated. One method was presented in [1] which is transfer printing of CYCLOTENE ® 3000 Resin from a help wafer to topography features of the device wafer. Although very good results were obtained, the method is restricted to applications with significant topography to enable the transfer printing. In this work we focus on a new structuring method for non-cured BCB layers formed from CYCLOTENE ® 3000 Resin. The layers were spin coated, baked and subsequently patterned using a 248 nm excimer laser stepper. The system features a 2.5× mask projection with a resulting exposure field of 6.5 × 6.5 mm2 and allows a direct ablation patterning of polymers. By using this method bond frame structures were patterned into 5 μm thick BCB layers at 200 mm silicon wafers. The wafers with the structured adhesive were bonded at 80 °C and 0.2 MPa for 5 minutes with 200 mm glass wafers. The bonded wafer stacks were subsequently post bond batch cured at 190 °C. Wafer dicing and shear tests of the bonded structures revealed excellent mechanical robustness of the BCB bond frames. The paper will review the new BCB wafer bond processes for supporting short cycle times with special focus on the new patterning approach by laser ablation. Process flow description as well as systematical analysis of pattern reproducibility of the new structuring method is part of the discussion.

Impact of Top Die Thickness on Cu Pillar Fatigue in Exposed Die 3D Packages

Customer demand for more powerful, faster, and multifunctional electronic devices in lighter and smaller form factors is forcing the electronics industry to expand the edges of the packaging envelope. 3D packaging is a result of such initiatives. Logic and memory dice (or logic and logic dice) are stacked on top of one another and connected through vertical Through Silicon Vias (TSVs). 3D integration has several well documented benefits such as lower power consumption, higher bandwidth, and low latency, to name a few. An added benefit of such a packaging scheme is that it reduces overall package dimensions compared to Multi-Chip Modules (MCMs). However, since the dies are stacked, total package height generally increases. One of the methods to minimize this effect is to use exposed die package construction. In this paper, exposed die 3D packages are examined and challenges associated with stacking thin dies with exposed molding are discussed. Exposed die package construction is of high importance to customers in mobile markets where power requirements and heat generation are low, but package thickness is of utmost importance. Data has been generated using a 20nm CPI (Chip Package Interaction) die which is packaged in a 3D format to study the impact of die stacking along with the presence of TSVs on Ultra Low-k (ULK) dielectrics. ULKs are commonly used in the Back End of Line (BEoL) during Si device wafer fabrication. Via middle TSV integration scheme is used to integrate TSVs in the CPI chip and a face-to-back (F2B) approach is used to assemble the top die on the CPI chiplet. The top die is mechanical in nature with Cu micro pillars and a few metal layers to form daisy chain structures when joined to the backside of TSV die. The CPI wafers are bumped on the frontside using Cu pillars and the wafers are then thinned to ~50um. The TSVs are carefully exposed from the wafer backside and wettable landing pads are patterned on the backside of the thinned wafer so as to align with the Cu micro pillars on the front side of top die. Two different thicknesses of top dies are used to study the impact of top die thickness on overall package warpage and Si-to-substrate interconnect reliability. Assembly is performed by first bonding the front side of TSV CPI chip to a substrate, and then by bonding the front of the top dies to the back of the bottom (TSV) die. The 3D packages were subjected to a variety of package level stresses and the reliability results will be presented. The effect of top die thickness is analyzed using two die thicknesses. As the packages are stressed, it is evident that packages with thinner top die show higher package level warpage and greater Cu pillar fatigue. Various mold compounds are used to improve the package warpage and data will be presented.

Multi-sensitive temperature sensor platforms using aluminum nitride MEMS resonators

This paper presents three MEMS platforms that exhibit multiple thermal sensitivities and multi-frequency capabilities. Multiple sensors with a variety of operating frequencies and thermal sensitivities can co-exist in the same device wafer. Aluminum nitride is the active layer of the three platforms. The impact of stack and substrate modifications on the performance of test devices is discussed as well. To test the platforms’ performance, temperature sensors are realized using Lamb-acoustic-wave micro-electro-mechanical (MEMS) resonators, each one featuring a different thermal coefficient of frequency that scales with frequency. Resonators designed for frequencies between 200 MHz to 1.5 GHz operate at their first symmetric mode (S0) and feature first-order TCFs in the range from −12 up to −30 ppm °C−1 depending on the frequency and design. Furthermore, TCFs of devices can be tailored to get smaller values through process variations. The platforms exhibit high electromechanical performance, with quality factors in excess of 1500 and maximum effective coupling coefficient of 6.43% for radio frequency (RF) applications above 1 GHz.

A Theoretical Study on Post-It-Like Debonding Process for BCB Cap Transfer Packaging Based on FEM Simulation

This paper presents ANSYS finite-element method analysis of wafer-level Benzocyclobutene cap transfer packaging process utilizing simple and easy detachment of the carrier wafer. The detachment has been implemented through hydrophobic monolayer coating of Si carrier wafer surface before BCB cap patterning. Razor blade insertion between the Si carrier and device wafer is used to separate the BCB cap from the carrier wafer. The debonding is regarded as interfacial fracture between Si and BCB, and thus the monolayered interface is modeled with ANSYS cohesive zone model. BCB cap's deformation and resultant stress during the debonding are principal interests of the modeling as it determines whether the transfer succeeds or fails. For this purpose, typical load-displacement curves of crack analysis are studied to comprehend the debonding behavior of the BCB cap in the course of Si carrier detachment. It is found that the BCB cap size is a critical parameter for the debonding process as interfacial toughness is proportional to the BCB cap dimension. And thicker BCB cap is more efficient to the debonding in terms of necessary opening displacement and developed maximum stress. In addition, cap material property such as Young's modulus has significant effect on the debonding behavior.

Effect of Surface Energy Reduction for Nano-Structure Stiction

Nano-structure stiction during drying has often occurred due to scaling of semiconductor devices. For less stiction drying technology, lower surface tension liquids such as isopropyl alcohol (IPA) or super critical fluid (SCF) have been developed, but are lacking in enough performance or maturity for 300 mm leading-edge device wafer treatment. Thus, we have focused on the surface energy reduction process which enables separation of the once adhering structures. We have evaluated the effect of the surface energy on the stiction with both calculation and experimental data, and have successfully demonstrated that the surface energy reduction process can suppress high aspect-ratio nano-structure stiction.

Oxygen Control Challenge for Advanced Wet Processing

Introduction Novel approaches including integration schemes (e.g. FinFET RMG) and new materials (e.g. Ge and III-V) for production are being studied. The introduction of Ge for CMOS device has shown interest in terms of advantage in the electron and hole mobility. However the use of Ge in CMOS integration is a new challenge in wet processing due to the significant Ge loss caused by oxidizers in liquid. Previous studies had focused on how to improve the process hardware with respect to Dissolved Oxygen (DO) concentration in liquid and oxygen concentration in ambient in wet processing. [1] This study focuses on the effect of Low DO condition for integration schemes, particularly two types of defect formation are used as representative metrics for the performance: the voids on Ge and the trench-formation in RMG on doped Si. [2] Experimental procedures (1) DO concentration measurement: The DO concentration in room temperature UPW and HF (0.5%) flowing though perfluoroalkoxy (PFA) tubing was measured using a DO concentration cell (HACH LANGE, 31120E.04). HF (0.5%)was prepared by co-mixing HF (49%) and UPW in line. Oxygen sensor (TORAY, LC-850KS) was used to measure oxygen concentration in ambient. (2) Selective Ni removal deposited on Ge : The sample shown as Fig. 1(a) was used to examine the generation of Ge voiding caused by galvanic corrosion in processing by various conditions of DO concentration in HCl (0.37%) and oxygen concentration in ambient. The generation of voiding was determined by SEM (AMAT, SEMVision G3) after wet processing. (3) Dummy oxide removal in high-k last process integration: The sample shown as Fig. 1(b) was used to examine the generation of Si channel trenching in processing by various conditions of DO concentration in HF (1.5%) and oxygen concentration in ambient. The generation of Si channel trenching was determined by TEM (FEI, Tecnai F30). Wet processing and DO concentration measurement were performed on a SCREEN Semiconductor Solutions single wafer cleaning tool (SU-3100). Results and Discussion Equipment improvements: Two points are key to reduce DO concentration in chemicals. The first key point is DO control in liquid. Table 1 shows the DO concentration in chemical at Point of Use (POU) with / without N2 purge to chemical tank or degassing module in line. This result shows that N2 purge and degassing module were effective to reduce the DO concentration in chemical. The second point is oxygen control in the wafer ambient environment during wet processing. Fig. 2 shows the oxygen concentration in ambient by using a shield-plate close to the wafer to block the atmosphere locally in combination with a N2 supply. By using the shield-plate, the oxygen concentration was controlled with less than 10 ppm, which resulted in only 0.44 ppb of dissolved oxygen based on Henry’s law. This concentration does not impact the DO concentration in chemical. By combining these two elements, the DO concentration in processing chemical can be reduced to 25ppb (HF 0.5%). Process results: Fig. 3 shows the NiGe loss on blanket wafer after processing in dHCl. A significant reduction of NiGe loss is obtained with Low DO process (25ppb). The prevention of void occurrence on Ge bulk FinFET device wafers is reported for the selective etch with the hot HCl process with low DO condition. Fig. 4 shows that the reduction of DO concentration in dHF can suppress Si channel trenching occurrence in condition of over etching and expand the process window. Conclusions It has been shown that the prevention of voiding occurrence on Ge and Si channel trenching occurrence was demonstrated by processing device samples with normal chemical with consideration to reduce the level of DO. The following two elements, “DO concentration in liquid” and “oxygen concentration in ambient in processing” are the key factors to achieve the low DO concentration processing.

High-Throughput Multiple Dies-to-Wafer Bonding Technology and III/V-on-Si Hybrid Lasers for Heterogeneous Integration of Optoelectronic Integrated Circuits

Integrated optical light source on silicon is one of the key building blocks for optical interconnect technology. Great research efforts have been devoting worldwide to explore various approaches to integrate optical light source onto the silicon substrate. The achievements so far include the successful demonstration of III/V-on-Si hybrid lasers through III/V-gain material to silicon wafer bonding technology. However, for potential large-scale integration, leveraging on mature silicon complementary metal oxide semiconductor (CMOS) fabrication technology and infrastructure, more effective bonding scheme with high bonding yield is in great demand considering manufacturing needs. In this paper, we propose and demonstrate a high-throughput multiple dies-to-wafer (D2W) bonding technology which is then applied for the demonstration of hybrid silicon lasers. By temporarily bonding III/V dies to a handle silicon wafer for simultaneous batch processing, it is expected to bond unlimited III/V dies to silicon device wafer with high yield. As proof-of-concept, more than 100 III/V dies bonding to 200 mm silicon wafer is demonstrated. The high performance of the bonding interface is examined with various characterization techniques. Repeatable demonstrations of 16-III/V-die bonding to pre-patterned 200 mm silicon wafers have been performed for various hybrid silicon lasers, in which device library including Fabry-Perot (FP) laser, lateral-coupled distributed feedback (LC-DFB) laser with side wall grating, and mode-locked laser (MLL). From these results, the presented multiple D2W bonding technology can be a key enabler towards the large-scale heterogeneous integration of optoelectronic integrated circuits (H-OEIC).

Impact of substrate resistance and layout on passivation etch-induced wafer arcing and reliability

Wafer arcing, as a form of plasma-induced damage, occurs randomly, varies among different products and introduces problems into production yield and reliability. Conventional arcing theory is based on substrate conductive paths, for which the arcing frequency decreases as the substrate resistance increases. However, we observed the reverse result, i.e., silicon-on-insulator (SOI) and integrated passive device (IPD) wafers with high substrate resistance suffered a high frequency of passivation (PA) etch-induced arcing. In addition, the newly developed through silicon vias (TSV) interposer process for three-dimensional (3D) packaging also encountered a similar problem. To explain and solve these problems, we used substrates of different resistivities using the arcing-enhanced method to study this PA etch-induced wafer arcing phenomenon and revealed the mechanism underlying the effect of substrate resistance, the role of the seal ring, the root cause of the layout’s effect on arcing frequency and the impact on reliability. Next, we determined that the reduction in arcing relies on the simultaneous optimization of the process and the layout and observed that the reduction of the arcing source helps to improve product reliability. Finally, improvement methods and guidelines were proposed for both the process and the layout.

Thin Wafer Handling Using Mechanical- or Laser-Debondable Temporary Adhesives

The development of adhesives that enable handling, processing, and assembly of thin wafers and die is a key technical challenge for the realization of 3D devices. We will present on temporary adhesive technology for processing of thinned wafers that is amenable to either mechanical or laser-assisted debonding that can occur at room temperature. Temporary wafer bonding has emerged as the method of choice for handling silicon wafers during the thinning and high-temperature backside processing required for the manufacture of 3D device structures. Among the requirements for temporary wafer bonding materials to be used in high volume manufacturing are simple device and carrier wafer preparation, high-throughput wafer bonding, thermal stability to 300 °C or higher, and clean room-temperature release directly from the device wafer using either mechanical or laser-assisted debonding We will present successful temporary wafer bonding using a BCB (benzocyclobutene)-based material that can meet these requirements. The mode of adhesive release from a device wafer will be discussed in detail as it relates to wafer thinning and handling, and material physical properties and resistances will be expressed. Formulation requirements needed for successful debonding will be presented, with an emphasis on a laser-debonding scheme that utilizes either a 248nm or 308nm laser source capable of ablating a laser sensitive layer residing between a glass carrier and the temporary wafer bonding material. Successful room temperature tape-peeling of the adhesive film after ablation and carrier removal will be discussed.