Abstract
Wafer arcing, as a form of plasma-induced damage, occurs randomly, varies among different products and introduces problems into production yield and reliability. Conventional arcing theory is based on substrate conductive paths, for which the arcing frequency decreases as the substrate resistance increases. However, we observed the reverse result, i.e., silicon-on-insulator (SOI) and integrated passive device (IPD) wafers with high substrate resistance suffered a high frequency of passivation (PA) etch-induced arcing. In addition, the newly developed through silicon vias (TSV) interposer process for three-dimensional (3D) packaging also encountered a similar problem. To explain and solve these problems, we used substrates of different resistivities using the arcing-enhanced method to study this PA etch-induced wafer arcing phenomenon and revealed the mechanism underlying the effect of substrate resistance, the role of the seal ring, the root cause of the layout’s effect on arcing frequency and the impact on reliability. Next, we determined that the reduction in arcing relies on the simultaneous optimization of the process and the layout and observed that the reduction of the arcing source helps to improve product reliability. Finally, improvement methods and guidelines were proposed for both the process and the layout.
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