Behavior of copper contamination on backside damage for ultra-thin silicon three dimensional stacking structure

Abstract

Bumpless interconnects and ultra-thinning of 300mm wafers for three-dimensional stacking technology have been studied. In our previous work, thinning effects using device wafers <10μm thick were reported. No degradation occurred in the retention time even in a 4-μm-thick DRAM wafer. In this study, the behavior of Cu contamination on a <3-μm-thick DRAM wafer was investigated. The wafer was thinned down by coarse (#320 grit size) grinding and fine (#2000 grit size) grinding. This thinning condition had 200-nm-thick ground damage remaining for the gettering effect. The DRAM wafer was intentionally contaminated with Cu on the damaged layer, and 250°C-60min of heating was carried out during adhesive bonding and de-bonding. Degradation in the device characteristics was found. However, the analytical results indicated that the Cu did not diffuse into the thin Si. Thus, a Cu contaminated blanket wafers having a damaged layer were prepared and annealed until 1000°C-30min. Secondary ion mass spectroscopy, transmission electron microscopy and positron annihilation spectroscopy were evaluated. The Cu was trapped in the vacancy-type defects of the 200nm damaged layer until a 700°C anneal. After an 800°C anneal, the Cu was eliminated on the damaged surface because of the Si recrystallization. The gettering ability of the damaged layer is suitable for 3D multi-level stacking regarding thermal stability.