Impact of back-grinding-induced damage on Si wafer thinning for three-dimensional integration

Abstract

Ultrathin wafers, which enable the low-aspect-ratio through-silicon vias to be formed easily, are indispensable for bumpless three-dimensional (3D) stacking. To clarify thinning-induced damage in detail, atomic-level defects occurring during wafer thinning and due to mechanical stress at microregions of the fracture surface have been studied. Such damage was evaluated by µ-Raman spectroscopy, laser microscopy, transmission electron microscopy, and positron annihilation spectroscopy. Coarse (#320 grit) grinding causes a roughly 500 MPa compressive stress, resulting in the formation of a less than 5 µm defect layer. Fine (#2000 grit) grinding enables the formation of a plane surface and reduces the stress to 100–200 MPa. However, a damaged layer of 200 nm still remains and an almost 100-nm-thick layer of vacancy-type defects exists. After chemical mechanical polishing (CMP), a stress-free surface was obtained and no defects were found except atomic-level vacancies, which were detected in a layer of 4 nm thickness after 1 µm CMP.