Manufacturable 300mm Wafer Thinning for 3D Interconnect Applications

Abstract

Abstract3D interconnect wafer-to-wafer or die-to-wafer integration requires a wafer thinning operation to expose copper (Cu)-filled through-silicon vias (TSVs) from the backside of the wafer. The wafer thinning flow uses edge trim, backgrind, backpolish, and chemical mechanical polishing (CMP). This paper presents an overview of the wafer grinding process. We have demonstrated the capability to edge-trim and backgrind 300 mm TSV and non-TSV wafers down to 30 microns (μm) while bonded to a handle wafer. TSV wafers were further processed on a CMP tool to remove the last few microns of Si, exposing the Cu-filled TSVs. Metrology techniques were used to inspect and measure the wafer edge trim and final thinned wafer thickness. The quality of the thinned wafer was characterized by atomic force microscopy (AFM) to observe surface roughness and by transmission electron microscopy (TEM) to quantify crystalline damage below the surface of the thinned wafer. Further characterization included measuring wafer thickness, total thickness variation (TTV), bow, and warp. Exposed TSVs were characterized by laser microscope to measure the height of Cu protrusions. These critical elements of a manufacturing-worthy 300 mm wafer thinning process for 3D are discussed.