Channel Length Devices Research Articles

Large-scale sub-5-nm vertical transistors by van der Waals integration

Vertical field effect transistor (VFET), in which the semiconductor is sandwiched between source/drain electrodes and the channel length is simply determined by the semiconductor thickness, has demonstrated promising potential for short channel devices. However, despite extensive efforts over the past decade, scalable methods to fabricate ultra-short channel VFETs remain challenging. Here, we demonstrate a layer-by-layer transfer process of large-scale indium gallium zinc oxide (IGZO) semiconductor arrays and metal electrodes, and realize large-scale VFETs with ultra-short channel length and high device performance. Within this process, the oxide semiconductor could be pre-deposited on a sacrificial wafer, and then physically released and sandwiched between metals, maintaining the intrinsic properties of ultra-scaled vertical channel. Based on this lamination process, we realize 2 inch-scale VFETs with channel length down to 4 nm, on-current over 800 A/cm2, and highest on-off ratio up to 2 × 105, which is over two orders of magnitude higher compared to control samples without laminating process. Our study not only represents the optimization of VFETs performance and scalability at the same time, but also offers a method of transfer large-scale oxide arrays, providing interesting implication for ultra-thin vertical devices.

Evolution and performance analysis of quantum well FinFET for 3 nm technology node with type-II strained tri-layered hetero-channel system

3D FinFETs are meticulously scaled down to sub-14 nm leading to reemerging undesirable characteristics namely increased Drain Induced Barrier Leakage (DIBL), higher subthreshold swing and excessive leakage currents. This inhibits the scaling of FinFETs and research suggests probable utilization of strained silicon technology in FinFETs to improve the on currents and transconductance of the nano devices. The emergence of quantum effects including velocity overshoot and carrier confinement severely affects the electrical characteristics at sub-10 nm channel length devices. Therefore, amalgamation of strained silicon prove to be a boon in FinFETs while being at par with the proposed 3 nm technology node of IRDS 2018, and designing to develop reliable devices at 08 nm gate length is the requisite. Thus, exploring the design and performance investigation of novel 08 nm Quantum Well FinFETs (QW-FinFETs) incorporating a tri-layered strained silicon Heterostructure-On-Insulator (HOI)are proposed with distinct channel dimensions which are analyzed and compared with existing devices. The optimum QW-FinFET device developed for 3 nm technology node of IRDS 2018 achieved a ∼25% enhancement in drain currents with Device D2 portraying almost ∼103% escalations in electron mobility on account of ballistic transport of charge carriers without scattering and enriching the performance for the future generation of device resulting in faster switching operation in sub-nano regime.

Tunable negative differential resistance behavior in the nitrogen-doped zigzag GeSe nanoribbon based single-gate field effect transistor

This article presents a theoretical study on the negative differential resistance (NDR) behavior of a bilaterally hydrogen-passivated Zigzag GeSe nanoribbon based single-gate field-effect transistor. It is focused on a 5-nm channel length device, and the study utilizes a simulation calculation that combines the density functional theory and non-equilibrium Green’s function. In this study, a nitrogen atom is introduced as a substitutional dopant to replace the Ge atom in the source and drain regions of the GeSe field-effect transistor to created special symmetry structure. The numerical results demonstrate that the current peak-to-valley ratio (PVR) of the device can be effectively controlled by applying a gate voltage and up to 105 with the current peak value of 0.3 nA at room temperature (300 K). The device configuration described in this study meets the requirements of real-world industrial applications. These findings highlight the potential of GeSe Zigzag nanoribbon for future electronic device applications at nanoscale.

Bottom-up synthesis of mesoscale nanomeshes of graphene nanoribbons on germanium

The synthesis of functional graphene nanostructures on Ge(001) provides an attractive route toward integrating graphene-based electronic devices onto complementary metal oxide semiconductor-compatible platforms. In this study, we leverage the phenomenon of the anisotropic growth of graphene nanoribbons from rationally placed graphene nanoseeds and their rotational self-alignment during chemical vapor deposition to synthesize mesoscale graphene nanomeshes over areas spanning several hundred square micrometers. Lithographically patterned nanoseeds are defined on a Ge(001) surface at pitches ranging from 50 to 100 nm, which serve as starting sites for subsequent nanoribbon growth. Rotational self-alignment of the nanoseeds followed by anisotropic growth kinetics causes the resulting nanoribbons to be oriented along each of the equivalent, orthogonal Ge⟨110⟩ directions with equal probability. As the nanoribbons grow, they fuse, creating a continuous nanomesh. In contrast to nanomesh synthesis via top-down approaches, this technique yields nanomeshes with atomically faceted edges and covalently bonded junctions, which are important for maximizing charge transport properties. Additionally, we simulate the electrical characteristics of nanomeshes synthesized from different initial nanoseed-sizes, size-polydispersities, pitches, and device channel lengths to identify a parameter-space for acceptable on/off ratios and on-conductance in semiconductor electronics. The simulations show that decreasing seed diameter and pitch are critical to increasing nanomesh on/off ratio and on-conductance, respectively. With further refinements in lithography, nanomeshes obtained via seeded synthesis and anisotropic growth are likely to have superior electronic properties with tremendous potential in a multitude of applications, such as radio frequency communications, sensing, thin-film electronics, and plasmonics.

Performance improvement of Hf0.45Zr0.55O x ferroelectric field effect transistor memory with ultrathin Al–O bonds-modified InO x channels

Ferroelectric field effect transistor (FeFET) memories with hafnium zirconium oxide (HZO) ferroelectric gate dielectric and ultrathin InO x channel exhibit promising applicability in monolithic three-dimensional (M3D) integrated chips. However, the inferior stability of the devices severely limits their applications. In this work, we studied the effect of single cycle of atomic-layer-deposited Al–O bonds repeatedly embedded into an ultrathin InO x channel (∼2.8 nm) on the Hf0.45Zr0.55O x FeFET memory performance. Compared to the pure InO x channel, three cycles of Al–O bonds modified InO x channel (IAO-3) generates a much larger memory window (i.e. drain current ratio between the programmed and erased devices) under the same program conditions (+5.5 V/500 ns), especially after post-annealing at 325 °C for 180 s in O2 (1238 versus 317). Meanwhile, the annealed IAO-3 FeFET memory also shows quite stable data retention up to 104 s, and much more robust program/erase stabilities till 105 cycles. This is because the modification of strong Al–O bonds stabilizes the oxygen vacancies and reduces the bulk trap density in the channel. Furthermore, it is indicated that the program and erase efficiencies increase gradually with reducing the channel length of the memory device. By demonstrating markedly improved performance of the HZO FeFET memory with the ultrathin IAO-3 channel, this work provides a promising device for M3D integratable logic and memory convergent systems.

Current Boosting of Self‐Aligned Top‐Gate Amorphous InGaZnO Thin‐Film Transistors under Driving Conditions

AbstractOxide semiconductor transistors control the brightness and color of organic light‐emitting diode (OLED) displays in large‐screen televisions to portable telecommunications devices. Oxide semiconductor thin‐film transistors under driving conditions are required to maintain a steady current through the OLED for constant illuminance. Interestingly, for driving conditions under strong saturation where both gate and drain bias are high, a boosting phenomenon of the drain current is discovered, even with compensation of the threshold voltage. In this paper, the current boosting effect of self‐aligned InGaZnO transistors under driving conditions is comprehensively investigated. Based on experimental extraction methods, two distinct regions within the device are identified: an electron‐capture‐dominant region including electron trapping in the gate insulator and O–O dimer bond‐breaking, and an electron‐emission‐dominant region caused by peroxide formation. A dual‐transistor‐in‐series model is proposed, where each region is modeled as a local transistor. The current boosting phenomena as a function of time are well‐reproduced for various channel length devices, which validate the accuracy of the model. Better understanding of the underlying mechanisms enables increased effectiveness of compensation schemes for transistors under long‐term current‐driving conditions.

Semiconducting SWCNT Photo Detector for High Speed Switching Through Single Halo Doping

The method opted for accuracy, and no existing studies are based on this method. A design and characteristic survey of a new small band gap semiconducting Single Wall Carbon Nano Tube (SWCNT) Field Effect Transistor as a photodetector is carried out. In the proposed device, better performance is achieved by increasing the diameter and introducing a new single halo (SH) doping in the channel length of the CNTFET device. This paper is a study and analysis of the performance of a Carbon Nano Tube Field Effect Transistor (CNTFET) as a photodetector using the self-consistent Poisson and Green function method. The 2D self-consistent Poisson and Green’s function method for various optical intensities and wavelength simulate this proposed photodetector. The performance study is based on the simulation of drain current, transconductance, sub-threshold swing, cut-off frequency, gain, directivity, and quantum efficiency under dark and illuminated conditions. These quantum simulation results show that cut-off frequency increases while there is an increase in diameter. The proposed SH-CNTFET provides better performance in terms of higher gain and directivity than conventional CNTFET (C-CNTFET). This device will be helpful in optoelectronic integrated circuits (OEIC) receivers due to its superior performance.

THz detection and amplification using plasmonic field effect transistors driven by DC drain currents

We report on the numerical and theoretical results of sub-THz and THz detection by a current-driven InGaAs/GaAs plasmonic field-effect transistor (TeraFET). New equations are developed to account for the channel length dependence of the drain voltage and saturation current. Numerical simulation results demonstrate that the effect of drain bias current on the source-to-drain response voltage (dU) varies with the device channel length. In a long-channel TeraFET where plasmonic oscillations cannot reach the drain, dU is always positive and rises rapidly with increasing drain current. For a short device in which plasmonic oscillations reach the drain, the current-induced nonuniform electric field leads to a negative response, agreeing with previous observations. At negative dU, the amplitude of the small-signal voltage at the drain side becomes larger than that at the source side. Thus, the device effectively serves as a THz amplifier in this condition. Under the resonant mode, the negative response can be further amplified near the resonant peaks. A new expression of dU is proposed to account for this resonant effect. Based on those expressions, a current-driven TeraFET spectrometer is proposed. The ease of implementation and simplified calibration procedures make it competitive or superior compared with other TeraFET-based spectrometers.

Analytical subthreshold current model of the dual-material tri-gate (DMTG) MOSFET and its application for subthreshold logic gate

Multi-gate MOSFETs are considered for realizing ultra-low-power circuits due to their superior channel control capability and short channel effect (SCE) resistance. To achieve this goal, it is necessary to establish a suitable compact device circuit model for them. However, current research focuses more on single-material multi-gate MOSFET, and there is no research report on dual-material logic gates. In this work, we develop a subthreshold current model for dual-material tri-gate (DMTG) MOSFET. It is found that the gate metal close to the source can affect the subthreshold characteristics of the transistor to a greater extent. Moreover, combined with the equivalent transistor model, the noise margin (NM) model of the subthreshold inverter composed of DMTG MOSFETs is developed. The nearly equal NM can be obtained by equal NM design (END). An appropriate work function can be selected through END to obtain the optimal NM when designing the inverter. The NM under different device geometric parameters is given, and the simulation result shows that the model accuracy reaches 98%. Finally, the effect of DMTG structure on the device drain induced barrier lowering (DIBL) is given, which effectively reduces DIBL by 42%. These models still remain high accuracy when the device channel length shrink down to 20 nm, which provide the possibility for DMTG MOSFET to be effectively applied to ultra-low-power circuits.

An optimized nanoscale Quasi-Ballistic DG MOSFET model with diffusive carrier scattering dependency

ABSTRACT The work proposes a physically accurate quasi-ballistic drain current model valid for Double Gate (DG) MOSFETs in the nanoscale regime. The proposed quasi-ballistic model considers the carrier scattering physics and includes both ballistic and diffusive transport. Based on the concepts of scattering theory, a semi-empirical approach is used to determine the diffusive carrier scattering at the critical channel length as a function of drain bias. A generalised three region scale length model is applied to the proposed device structure with arbitrary dielectric constants and oxide thicknesses to examine the device channel length scaling limits. The significance of Eigen values and the scale length equations applicable for the proposed device structure is discussed. The drain current model essentially captures the key signature effect observed in rigorously scaled short channel devices. Further, the proposed quasi-ballistic model demonstrates its physical aptness and optimal accuracy when compared with other similar recent works. The model results obtained are verified using numerical simulations and are found to exhibit excellent continuity in all regions of the device operation.

Negative-to-Positive Differential Resistance Transition in Ferroelectric FET: Physical Insight and Utilization in Analog Circuits.

In this article, for the first time, we explained a detailed physical insight for negative differential resistance (NDR) to positive differential resistance (PDR) transition in a ferroelectric (FE)-based negative capacitance (NC) FET and also its dependence on the device terminal voltages. Using extensive well-calibrated TCAD simulations, we have investigated this phenomenon on fully depleted silicon on insulator (FDSOI)-NCFET. The NDR-to-PDR transition occurs due to FE layer capacitance changes from a negative to positive state during channel pinchoff. This, in turn, results in a valley point in the output characteristic ( IDS - VDS ) at which the output resistance is infinite. We also found that we could alter the valley point location by modulating the vertical electric field through the FE layer in the channel pinchoff region using body bias ( VBB ). The interface oxide charges also impacted the NDR to PDR transition, and a positive interface charge results in faster NDR to PDR transition. Furthermore, we have utilized the modulation in the NDR-to-PDR transition due to VBB for designing a current mirror. Results show that the output current ( IOUT ) variation due to VDS reduces from ~8% to ~2% with VBB . We have also designed a single-stage common source (CS) amplifier and provided design guidelines to achieve a higher gain in the NDR region. The results obtained using a small-signal model of the FDSOI-NCFET demonstrate that ~25% higher gain can be achieved with the discussed design guidelines in the NDR region compared to the transition region of IDS - VDS . We have also explored the device scaling effect on the amplifier gain and found that ~ 2.23× gain can be increased with smaller channel length and higher device width.

DESIGN AND ANALYSIS OF TRI-LAYERED STRAINED CHANNEL DG SHOI FET AT 14 NM

Semiconductor device scaling in deep sub-nm scale strained silicon technology-based double-gate (DG) field effect transistors (FETs) with strained channel developed at 14-nm channel length provides a promising substitute in restricting performance degradation beyond 22 nm technology node. The newly designed double-gate field effect transistor on the insulator is comprised of a three-layer structure s-Si/s-SiGe/s-Si, which is directly deployed in the channel region. But the thickness of channel layers is varied to that in the previously designed 22-nm channel length device, which results in mobility enhancement in the channel region. The linear drive current enhancement is measured analytically with incorporation of the effect of strain on mobility of the charge carrier. Due to additional control with two gates in the device, the charge carrier flows from source to drain, experiencing ballistic transport through the short channel. The DG FET with strained channel designed on a 14-nm technology node provides 53.5% enrichment in drain current to that of a 22-nm channel length with acceptable leakage current.

Impact of Hot Carrier Aging on the 1/f and Random Telegraph Noise of Short-Channel Triple-Gate Junctionless MOSFETs

The low-frequency noise of short channel triple-gate junctionless (TG JL) MOSFET has been investigated in the frequency and time domains before and after hot carrier aging (HCA). The objective of this work is to investigate the interaction between HCA/flicker noise (1/f noise) and random telegraph noise (RTN) of short channel length device (L = 25 nm) exhibiting high density of interface traps. Significant variation in the noise spectral density has been observed between the fresh and the stressed device, related to the occurrence of generation-recombination (g-r) noise. Gate voltage dependence of g-r noise has been observed, assigned to gate dielectric traps and interface traps. In the fresh device, the noise is dominated by 1/f noise and multiple level RTN due to interface traps. In the stressed device, the 1/f noise is overlaid by multiple level RTN due to traps in the gate dielectric and at the gate insulator-silicon interface. The multiple level RTN relative amplitude can be described by the generic carrier number with correlated mobility fluctuations model as for the two level RTN detected in long channel devices (L = 65 and 95 nm).

Flexible high-performance organic thin film transistors and PMOS inverters: Trap controlled grain boundaries and contact resistance effect in different channel length devices

Printed high-performance organic thin film transistors (OTFTs) are fabricated on flexible polyethylene naphthalate (PEN) substrate for low-voltage operation. Gate, source and drain electrodes are inkjet-printed using conductive silver ink, while chemical vapor deposition grown parylene is used as dielectric layer. We used a blend of 2,7-dihexyl-dithieno[2,3-d;2′,3′-d′]benzo[1,2-b;4,5-b′]dithiophene (DTBDT-C6) and polystyrene (PS), for active p-type organic semiconducting material, and deposited by a dispenser system to achieve 0.66 cm2/Vs mobility at VGS = −6 V. For a set of 30 OTFT devices, the uniformity in device characteristics is illustrated by plotting the histograms for on current, mobility, and threshold voltage (VTh). Mobility decrease for small channel length due to greater contribution of contact resistance, while negative VTh shift occurs because of the generation of hole traps at dielectric-semiconductor interface attributed to moisture present. Electron traps on grain boundaries of the active semiconducting layer causes positive shift in VTh. By using these high mobility OTFT devices, two different low-voltage operation PMOS (P-channel metal-oxide-semiconductor) inverters are fabricated for which high signal gain value of 24.86 is achieved at VDD = −5 V.

Ground Plane Electrostatically Doped Junctionless Tunnel Field Effect Transistor: Process Immune Design for Suppressed Ambipolarity

The incorporation of a highly doped Si layer below the Si film, termed as the ground plane, in the electrostatically doped junctionless tunnel field effect transistor (ED-JLTFET) with high-K gate stack. This allows the conceptualization and realization of highly reduced ambipolar behaviour with enhancement in the drive current. The deployed GP sinks the electric field induced at drain side, increases the effective channel length for the short channel devices, prevents the direct source-to-drain tunneling and also the channel-to-drain tunneling in reverse direction at negative gate voltages. A significant reduction of sub-threshold slope and DIBL is also reported for the considered device structure. Using a calibrated exhaustive TCAD study, the detailed sensitivity analysis is also carried for the proposed device with the parametric sweep method. Further, the device analog/RF performance is also comprehensively examined for its high frequency operations. Interestingly, it is also observed that the deployment of this GP also results in better volume depletion. Moreover, due to electrostatically doped structure, the reported device is also expected to have a lower thermal budget, immune towards the random dopant fluctuations (RDFs) effects and tolerant towards the velocity degradation effects as well. Hence, the reported device is a potential candidate for implementing ultra low power steep switching transistors.

P‐1.5: High‐Voltage characteristics of Top‐Gate Amorphous InGaZnO Thin‐Film Transistors

In this paper, we investigated high‐voltage characteristics of topgate amorphous InGaZnO thin‐film transistors. Results indicate that the saturation current decreases at high drain bias. Moreover, the threshold voltage (Vth) positive shift after device biased at the high drain voltage and the shift magnitude become larger at shorter channel length devices. These observations are attributed to the fact that hot electrons were produced due to the strong drain to source electric field and trapped in the gate insulator. The device performance was recovered after 1000‐s negative gate bias at 60 °C.

Contact resistance corrected-electrical characteristics with channel length effects in π-conjugated small-molecule benzanthracene organic thin film transistors

In this work, bottom-contact p-type organic thin-film transistors based on small-molecule benzanthracene with various channel lengths were fabricated, characterized, and theoretically investigated. The fabricated devices showed a pronounced shift for threshold voltage as the function of channel length. Electrical parameters characterizing fabricated devices have been systematically evaluated as a function of channel length with and without contact resistance in the calculation. Contact resistance (Rc) and channel resistance (Rch) are extracted individually using the transfer line method (TLM) for output characteristic curves that were done only at low drain voltage (linear regime). The effect of contact resistance on the values of various OTFTs parameters is more pronounced in short channel length devices. The obtained results revealed that the linear regime's corrected mobilities of short channel devices are about 15% smaller than uncorrected mobility. Comparatively, the corrected threshold voltage values were found to be nearly close to uncorrected values for all channel lengths. The analytical model was also applied to reproduce output characteristics in the linear regime of different channel lengths devices with or without contact resistance. It was found that the calculated results were in good agreement with the measured results (when considering the effect of contact resistance), which confirms that the used model can correctly describe the charge transport in these kinds of devices.

Influence of temperature and dimension in a 4H-SiC vertical power MOSFET

A study of the impact of dimension and temperature on a state of the art 4H-SiC power vertical DMOSFET has been carried out using drift-diffusion calculations in conjunction with electrical characterizations to extract physical parameters and doping profiles in a 6 μm channel length device. The model presented in this paper includes the effect of trapping in the channel/oxide interface. Using these parameters, the performance of corresponding lateral and vertical scaled devices are studied. Electrothermal simulations showing self-heating effects are also carried out. The results are qualitatively discussed with the help of an analytical physical model, which considers the interplay between the different device resistances. At low drain bias, the drain current is increased by 42.86% (I D = 5 A at V G = 20 V) when reducing the dimension vertically, whereas it is decreased by 28.57% (I D = 2.5 A at V G = 20 V) when reducing the dimension laterally. These effects are enhanced at high drain bias. In addition, the effect of dimension reduction for breakdown voltage, electric field and impact ionization is investigated. A substantial reduction in breakdown voltage was found when the vertical dimensions were decreased as compared to the lateral dimensions.

Highly photoresponsive visible light photodetector using nano PbS thin film on paper

In this work, we demonstrated highly efficient visible light photodetector fabricated using spray coated nano lead sulfide (PbS) thin film at 100 0C on 300 GSM paper with pencil drawn electrodes. The effect of variations in channel length on the photoconducting properties of the nano PbS thin films was investigated. The results revealed that the device with 1 mm channel length has better photosensitive and responsive properties compared with other channel length devices. A proto type photodetector device fabricated in the laboratory using optimized nano PbS thin film shows photosensitivity of 102 and fast rise / decay time of 14.7 / 6.3 ms at 20 V. The results demonstrate the potential of application of nano PbS thin films for photodetectors and optical switches, which have high sensitivity and fast response time applicable in optoelectronic device technology.

Lithography-free fabrication of low operating voltage and large channel length graphene transistor with current saturation by utilizing Li+ of ion-conducting-oxide gate dielectric

The large channel length graphene field-effect transistor (GFET) can outperform its competitors due to its larger active area and lower noise. Such long channel length devices have numerous applications, e.g., in photodetectors, biosensors, etc. However, long channel length graphene devices are not common due to their semi-metallic nature. Here, we fabricate large channel length (up to 5.7 mm) GFETs through a simple, cost-effective method that requires thermally evaporated source-drain electrode deposition, which is less cumbersome than the conventional wet-chemistry based photolithography. The semiconducting nature of graphene has been achieved by utilizing the Li+ ion of the Li5AlO4 gate dielectric, which shows current saturation at a low operating voltage (∼2 V). The length scaling of these GFETs has been studied with respect to channel length variation within a range from 0.2 mm to 5.7 mm. It is observed that a GFET of 1.65 mm channel length shows optimum device performance with good current saturation. This particular GFET shows a “hole” mobility of 312 cm2 V−1 s−1 with an on/off ratio of 3. For comparison, another GFET has been fabricated in the same geometry by using a conventional SiO2 dielectric that does not show any gate-dependent transport property, which indicates the superior effect of Li+ of the ionic gate dielectric on current saturation.