Ground Plane Electrostatically Doped Junctionless Tunnel Field Effect Transistor: Process Immune Design for Suppressed Ambipolarity

Abstract

The incorporation of a highly doped Si layer below the Si film, termed as the ground plane, in the electrostatically doped junctionless tunnel field effect transistor (ED-JLTFET) with high-K gate stack. This allows the conceptualization and realization of highly reduced ambipolar behaviour with enhancement in the drive current. The deployed GP sinks the electric field induced at drain side, increases the effective channel length for the short channel devices, prevents the direct source-to-drain tunneling and also the channel-to-drain tunneling in reverse direction at negative gate voltages. A significant reduction of sub-threshold slope and DIBL is also reported for the considered device structure. Using a calibrated exhaustive TCAD study, the detailed sensitivity analysis is also carried for the proposed device with the parametric sweep method. Further, the device analog/RF performance is also comprehensively examined for its high frequency operations. Interestingly, it is also observed that the deployment of this GP also results in better volume depletion. Moreover, due to electrostatically doped structure, the reported device is also expected to have a lower thermal budget, immune towards the random dopant fluctuations (RDFs) effects and tolerant towards the velocity degradation effects as well. Hence, the reported device is a potential candidate for implementing ultra low power steep switching transistors.