Evolution and performance analysis of quantum well FinFET for 3 nm technology node with type-II strained tri-layered hetero-channel system

Abstract

3D FinFETs are meticulously scaled down to sub-14 nm leading to reemerging undesirable characteristics namely increased Drain Induced Barrier Leakage (DIBL), higher subthreshold swing and excessive leakage currents. This inhibits the scaling of FinFETs and research suggests probable utilization of strained silicon technology in FinFETs to improve the on currents and transconductance of the nano devices. The emergence of quantum effects including velocity overshoot and carrier confinement severely affects the electrical characteristics at sub-10 nm channel length devices. Therefore, amalgamation of strained silicon prove to be a boon in FinFETs while being at par with the proposed 3 nm technology node of IRDS 2018, and designing to develop reliable devices at 08 nm gate length is the requisite. Thus, exploring the design and performance investigation of novel 08 nm Quantum Well FinFETs (QW-FinFETs) incorporating a tri-layered strained silicon Heterostructure-On-Insulator (HOI)are proposed with distinct channel dimensions which are analyzed and compared with existing devices. The optimum QW-FinFET device developed for 3 nm technology node of IRDS 2018 achieved a ∼25% enhancement in drain currents with Device D2 portraying almost ∼103% escalations in electron mobility on account of ballistic transport of charge carriers without scattering and enriching the performance for the future generation of device resulting in faster switching operation in sub-nano regime.