Exploration and development of tri-gate quantum well barrier FinFET with strained nanosystem channel for enhanced performance

Abstract

With FinFETs scaled below 20 nm technology nodes, nanodevices are not immune to Short Channel Effects (SCEs) leading to reduced carrier mobility, transconductance and finally degrading the drive current. Quantum effects such as carrier confinement and velocity overshoot plays vital role at device dimensions of 10 nm, divulging severe anomalies in the electrical characteristics. So, incubating strain engineering to maintain the required scaling stands the lone recourse for exploring and developing novel Nanoelectronic devices. Consequently, integrating Trigate (TG) Quantum Well Barrier (QWB) FinFET with tri-layered strained Hetero-structure on Insulator (HOI) channel is proposed. A diverse set of novel devices at 10 nm gate length are investigated developing the optimized QWB device with 33.3% drain current enhancement. The subsequent QWB FinFET (Device B) shows reduced SCEs with ∼90% escalations in electron mobility and ∼44% augmented device performance to be the future generation of devices having faster switching operation in sub-nano regime.