Digital Logic Design Research Articles

Utilization of Negative-Capacitance FETs to Boost Analog Circuit Performances

Negative-capacitance FETs (NCFETs) are a promising candidate for low-power circuits with intrinsic features, e.g., the steep switching slope. Prior works have shown potential for enabling low-power digital logic and memory design with NCFETs. Yet, it is still not quite clear how to harness these new features of NCFETs for analog functionalities. This article provides more insights into the circuit design space with new device characteristics and investigates its deployment in analog circuits, specifically, time-domain analog-to-digital converters (ADCs) and phase-locked loops (PLLs). We propose and optimize a novel digital-based clocked comparator and a capacitor-based voltage-to-time converter (VTC), which are essential building blocks in ADCs and PLLs. Evaluation results show beyond-FinFET comparison speed and enhanced linearity for the proposed NCFET-based clocked comparator and VTC, respectively. Such improvement is achieved by exploiting the steeper slope and increased output impedance of NCFETs. More details on design details and a discussion are provided in this article.

A Compact Adder and Reprogrammable Logic Gate Using Micro-Electromechanical Resonators With Partial Electrodes

In this brief, the design principles and experimental demonstration of a compact full adder along with a reprogrammable 4-input logic gate are presented. The proposed solution for implementation of digital circuits is based on a clamped–clamped micro-beam resonator with multiple split electrodes, in which the logic inputs tune the resonance frequency of the beam. This technique enables re-programmability during operation, and reduces the complexity of the digital logic design significantly; as an example, for a 64-bit adder, only 128 micro-resonators are required, compared to more than 1500 transistors for standard complementary metal–oxide–semiconductor (CMOS) architectures. We also show that an optimized simulated micro-resonator-based full adder is 45 times smaller than a CMOS mirror adder in 65-nm technology. While the energy consumption of this early generation of micro-resonator logic gates is higher than the CMOS solutions, we show that by careful device optimization and shrinking of the dimensions, femtojoules energy consumption and MHz operation, required by Internet of Things applications, are attainable.

New modified-majority voter-based efficient QCA digital logic design

ABSTRACTQuantum-dot cellular automata (QCA) is an emerging nanotechnology and a possible alternative solution to the limitation of complementary metal oxide semiconductor (CMOS) technology. One of the most attractive fields in QCA is the implementation of configurable digital systems. This article presents a novel multifunctional gate called the modified-majority voter (MMV). The proposed gate works on the explicit interaction of the cell characteristic property for the implementation of digital circuits. This prominent feature of the proposed gate reduces the maximum hardware cost and implements highly efficient QCA structures. To verify the functionality of the proposed gate, some physical proofs, truth table and computational simulation results are performed. These results assured the validity of the existence of the proposed gate. It also dissipates less energy which has been calculated under three separate tunnelling energy levels using the QCAPro tool. To prove the effectiveness of the proposed MMV gate, several optimal irreversible arithmetic circuits such as three-input XOR, half-adder and full-adder are proposed. The modular layouts are verified with the freely available QCADesigner tool version 2.0.3.

Implementation in Matlab & Tools Environment of Empirical Models of MOSFET-like CNTFETs for a Quick and Easy Design of the Next Generation Digital Electronic Circuits

In this paper it is proposed the implementation in Matlab & Tools environment, by using Simulink and Simscape plug-ins, of empirical models of the Carbon Nanotube Field Effect Transistor (CNTFET) in order to evaluate the capability of this very interesting design and simulation environment to easily design the most advanced generation of digital electronic circuits. Empirical models of electronic devices are particularly suitable for the Computer Aided Design (CAD) of digital electronic circuits. They are generally very compact, fast and accurate, without any physical approximation, and then they can be easily implemented in circuit simulators. The paper aims at describing the core of a possible CAD tool for digital circuits using CNTFETs, designed by the author, and at evaluating its suitability and usefulness by design examples. Therefore, they have been implemented two models of CNTFETs in Matlab & Tools environment and it has been performed the design of basic digital logic gates and memory elements. One of the two models has been developed by the author and already validated. The other model has been developed by valuable authors at Standford University and is used for comparisons. Results show the great usefulness of the empirical approach and of the Matlab & Tools environment for the quick and easy design of digital electronic circuits using CNTFETs.

Power efficient optimum design of the Reversible Plessey Logic Block of a field-programmable gate array

Reversible logic has captured significant attention in recent time for its reduced power consumption property which is one of the main concerns of digital logic design. Reprogram ability, higher speed, higher density, non-recurring engineering (NRE) costs, massive parallel operations and many other favoring factors have made prominent use of the Field-Programmable Gate Array (FPGA) in today's electronics world. In this paper, the most significant part of an FPGA, the Plessey Logic Block is designed in reversible manner with optimal parameters. On the way to design the proposed reversible Plessey Logic Block, each individual components such as reversible D-Latch, reversible Decoder, reversible Multiplexer, reversible Master-Slave Flip-Flop, reversible RAM are designed separately.. The proposed design of the individual parts is primarily optimized for the number of gates, garbage outputs, quantum cost and delay. In addition, area and power are optimized to ensure the power efficiency of the circuits. Two 4×4 reversible gates, namely HNF (Hafiz-Naz-Flip-Flop) gate and HND (Hafiz-Naz-Decoder) gate, are proposed to achieve the optimization goal. Moreover, proposed algorithms, lemmas and theorems certify the novelty of the proposed design. Compared to previous works, the proposed counter parts of Reversible Plessey Logic Block require less number of gates, garbage outputs, quantum cost and the delay. Finally, the proposed Reversible Plessey (4×2) Logic Block is compared with existing designs. The comparative result proves the efficacy and novelty of the proposed design showing improvement 51.62% in terms of number of transistor, 73.57% in terms of area (mm2) and 34.12% in terms of power (mW) with respect to the corresponding metrics of the best design in literature.

On compiling Boolean circuits optimized for secure multi-party computation

Secure multi-party computation (MPC) allows two or more distrusting parties to jointly evaluate a function over private inputs. For a long time considered to be a purely theoretical concept, MPC transitioned into a practical and powerful tool to build privacy-enhancing technologies. However, the practicality of MPC is hindered by the difficulty to implement applications on top of the underlying cryptographic protocols. This is because the manual construction of efficient applications, which need to be represented as Boolean or arithmetic circuits, is a complex, error-prone, and time-consuming task. To facilitate the development of further privacy-enhancing technology, multiple compilers have been proposed that create circuits for MPC. Yet, almost all presented compilers only support domain specific languages or provide very limited optimization methods. In this work (this is an extended and revised version of the paper ‘Secure Two-party Computations in ANSI C’ (Holzer et al., in: ACM CCS, 2012) that reflects the progress in secure computation and describes the current optimization tool chain of CBMC-GC) we describe our compiler CBMC-GC that implements a complete tool chain from ANSI C to circuit. Moreover, we give a comprehensive overview of circuit minimization techniques, which we have identified and adapted for the creation of efficient circuits for MPC. With the help of these techniques, our compilation approach allows for a high level of abstraction from the cryptographic primitives used in MPC protocols, as well as the complex design of digital circuits. By using the model checker CBMC as a compiler frontend, we illustrate the link between MPC, formal methods, and digital logic design. Our experimental results illustrate the effectiveness of the implemented optimizations techniques for various example applications. In particular, compared with other state-of-the-art compilers, we show that CBMC-GC compiles circuits from the same source code that are up to four times smaller.

Teaching Reform on Digital Circuit and Logic Design Course

Owning strong theoretical and practical performance, the “digital circuit and logic design” course plays a vital role in the electronic information speciality. Although the digital circuit and logic design course emphasizes the practical characteristics, there still ignores the linking with other courses in teaching process. In this paper, the teaching reform program is put forward by the project-driven methods to embody the course characteristics of the engineering application, then the course teaching reform indicates that it can better stimulate the students’ learning interest, train the students’ creative thinking and improve the students’ entrepreneurial ability, then train the excellent electronic information talents.

FPGA-based elastic in-circuit debugging for complex digital logic design

FPGA-based elastic in-circuit debugging for complex digital logic design

Area efficient digital logic NOT gate using single electron box (SEB)

The continuing scaling down of complementary metal oxide semiconductor (CMOS) has led researchers to build new devices with nano dimensions, whose behavior will be interpreted based on quantum mechanics. Single-electron devices (SEDs) are promising candidates for future VLSI applications, due to their ultra small dimensions and lower power consumption. In most SED based digital logic designs, a single gate is introduced and its performance discussed. While in the SED based circuits the fan out of designed gate circuit should be considered and measured. In the other words, cascaded SED based designs must work properly so that the next stage(s) should be driven by the previous stage. In this paper, previously NOT gate based on single electron box (SEB) which is an important structure in SED technology, is reviewed in order to obtain correct operation in series connections. The correct operation of the NOT gate is investigated in a buffer circuit which uses two connected NOT gate in series. Then, for achieving better performance the designed buffer circuit is improved by the use of scaling process.

FPGA-based elastic in-circuit debugging for complex digital logic design

In digital integrated circuit design, the emergence of intellectual property (IP) reuse technology reduces the complexity of system on chip (SoC) design, and makes the SoC have more and more powerful functions. Unfortunately, it also increases the verification difficulty, and extends the whole system design cycle. Aiming at the low efficiency of stimulating mechanism, the difficulty of real-time signal monitoring and non-reusability of module-level verification platform for IP design based on field-programmable gate array (FPGA), we propose a kind of elastic in-circuit debugging method for complex digital logic design so as to optimise the verification process. Based on the extension of traditional IP verification platform, we build the IP in-circuit debugging platform, which has some advantages such as elasticity, configurability, extensibility and humanisation. After verification of multiple IP instances, the results show that the method has strong universality and can improve the efficiency of IP verification.

Teaching Practice for CMOS Inverter and Transmission Gate

CMOS inverter and transmission gate are the basic logic gate circuits in digital logic design and its application. They are also the digital circuits with which students first come into contact. Correctly understanding the inverter and the gate is the basis of learning other logic gate circuits. From the question existed in NMOS inverter to the formation of CMOS inverter and transmission gate, heuristic and discussion-based teaching method is applied in the course teaching. The process of problem solving is presented by guiding the students to analyze problems step by step. The practice results have shown that students’ interest in learning the course has been improved, and that the knowledge of context and the related knowledge of mutual relations have been mastered.

Optimized design and performance analysis of novel comparator and full adder in nanoscale

AbstractIn a vastly rapid progress of very large scale integration (VLSI) archetype, it is the requirement of moment to attain a consistent model with swifter functioning speed and low power utilization. Quantum-dot Cellular Automata (QCA) is an inimitable transistorless computation approach that is based on semiconductor substantial and a substitute for customary CMOS and VLSI archetype at nanoscale point which comprises a better switching frequency, enhanced scale integration and small extent. In the design of digital logic, a comparator is the essential forming component which implements the resemblance of two numbers and a binary full adder is a major entity in digital logic systems. This paper deals with an expanded layout of reversible 1-bit comparator and proficient full adder without wire-crossing in QCA. The proposed layouts are significantly declined in terms of area and cell complexity, assessed to other layouts and clock cycle is retained at least. Quantum costs of the proposed circuits are es...

A Combinational Digital Logic Design Tool for Practice and Assessment in Engineering Education

As technology advances, computers are being used almost everywhere. In a 2013 US Census report (File and Ryan, 2014), 83.8% (up from 78.9% in 2012) of U.S. households reported owning a computer with 74.4% reporting internet use (73.4% high speed internet). In recent years, the shift in educational technologies has been moving towards gaming, more specifically serious gaming. Although this is an important trend, there is still much to be said about e-learning through a step-by-step interactive process using an online practice tool. This paper presents a detailed description of the Combinational Logic Design Tool (CLDT) (Morsi and Russell (2007). CLDT was designed and developed under the CCLI project, #0737242, funded by the National Science Foundation, which aimed to develop and disseminate a novel online practice tool for on demand review and assessment in Electrical and Computer Engineering education. The paper also reports on a formal assessment conducted in a Digital Logic Design Classroom and presents the results of this assessment.

Using software simulators to enhance the learning of digital logic design for the information technology students

ABSTRACTMaking the students understand the theoretical concepts of digital logic design concepts is one of the major issues faced by the academics, therefore the teachers have tried different techniques to link the theoretical information to the practical knowledge. Use of software simulations is a technique for learning and practice that can be applied to many different disciplines. Experimentation of different computer hardware components/integrated circuits with the use of the simulators enhances the student learning. The simulators can be rather simplistic or quite complex. This paper reports our evaluation of different simulators available for use in the higher education institutions. We also provide the experience of incorporating some selected tools in teaching introductory courses in computer systems. We justified the effectiveness of incorporating the simulators into the computer system courses by use of student survey and final grade results.

Towards the hierarchical design of multilayer QCA logic circuit

As a potential alternative to CMOS technology, Quantum-dot Cellular Automata (QCA) promises efficient digital design with high device density and low power dissipation in the future. This work targets the development of multi-layered architecture in the QCA framework with the goal to build an efficient methodology for QCA based digital logic design. A strategy for modelling, digital devices around QCA multiplexer is framed, which directs to the conception of complex digital circuits with high device density and low latency (i.e., more quick functioning). The proposed multilayer design also points to inherent aspects of radius of effect of QCA cells and the layer spacing in multilayer architecture. Minimum clock zone (2 clock) with high compaction (0.01μm2) is achieved for the multiplexer designed in QCA framework. A heuristic approach to synthesize multilayer synchronized QCA logic circuit is also proposed. Experimental results illustrate significant improvements in design level in terms of circuit area, cell count and clock over that of conventional design approaches.

Reversible Comparator Design Using Quantum Dot-Cellular Automata

ABSTRACTQuantum dot-cellular automata (QCA) emerge as a research area to design nanometre scale logic circuit. In digital logic design, a comparator is the fundamental building block that performs the comparison of two numbers. This paper deals with the design of reversible building block for 1-bit comparator and its implementation in QCA. An improved QCA layout of Feynman gate is also achieved. The QCA Feynman gate is denser and has low delay than the existing circuit. The proposed reversible comparator has quantum cost 9, whereas the QCA reversible comparator has the quantum cost 0.927. The quantum cost based comparison of the proposed QCA reversible comparator with conventional reversible comparator shows the cost effective circuit design in QCA. The simulation result matched the truth table of comparator which approves the functional capability of the proposed QCA layout of comparator. All the proposed layouts dissipate very low power.

Digital Logic Introduction Using FPGAs

The paper describes the adaptation of the Computer Architecture laboratory works given at the Faculty of Engineering in Foreign Languages from the University POLITEHNICA of Bucharest to the new trends in digital logic design. The laboratories are given in a gradual approach, starting with simulation, continuing with breadboard design and finishing with circuits made on perf-board. We are preparing now to complement the practical side of the laboratory with Field-Programmable Gate Array (FPGA) design, where the students will conceive, simulate, synthesize and implement the circuits already studied in the initial approach that used simulation followed by integrated circuits practical design.

A Web-Based Visualization and Animation Platform for Digital Logic Design

This paper presents a web-based education platform for the visualization and animation of the digital logic design process. This includes the design of combinatorial circuits using logic gates, multiplexers, decoders, and look-up-tables as well as the design of finite state machines. Various configurations of finite state machines can be selected to define the machine type, the state code, and the flip-flop type. Logic minimization with the K-map approach and the Quine McCluskey scheme is also supported. The tools, denoted as DLD-VISU, help students practice related topics in digital logic design courses. Also, instructors can use the tools to efficiently generate and verify examples for lecture notes or for homework problems and assignments. DLD-VISU was designed relying on a thorough investigation of related pedagogical aspects to define appropriate interactive graphical processes. The decision for a web-based solution, on the one hand, was motivated by making the tools available, portable, expandable, and at the same time transparent to the user. On the other hand, the advocated approach enables instructors to define access rules for their students to assure that students cannot use the tools to solve assessed homework problems or assignments before submission deadline. DLD-VISU supports self-assessment and reflects the student learning process using learning curves. The proposed platform was evaluated both in form of students' feedback as well as by analyzing the impact of using the tools on students' performance.

Verilog HDL Simulator Technology: A Survey

Digital logic design has become increasingly complex in multi-billion transistor VLSI. In order to model such a circuit, Verilog has emerged to be one of the most widely used Hardware Description Languages in digital VLSI design. Verilog's ability to model a circuit at different abstraction levels makes it a preferred mode of design entry starting from the conceptual stage till obtaining the final gate level netlist. At every stage along the development, simulations are inevitably needed to verify circuit correctness. Various forms of software and hardware assisted digital logic simulators were developed ever since the adoption of Verilog in the industry. With increasing circuit design density and complexity, major simulator vendors are struggling to improve simulation throughput in order to maintain quality and engineering cost of product development. Researchers are actively studying new improvements and approaches to keep simulators relevant. This paper surveys the research activities in Verilog simulator technologies as well as comparing every technology's strengths and weaknesses.

Approach to design a compact reversible low power binary comparator

Reversible logic has captured significant attention in recent time as reducing power consumption is the main concern of digital logic design. It consumes less power by recovering bit loss from its unique input-output mapping. In this study, the authors propose a reversible low power n -bit binary comparator. An algorithm is presented for constructing a compact reversible n -bit binary comparator circuit. The authors also propose two new reversible gates, namely, Babu-Jamal-Saleheen (BJS) and Hasan-Lafifa-Nazir (HLN) gates, to optimise the comparator. In addition, several theorems on the numbers of gates, garbage outputs, quantum cost, ancilla input, power, delay and area of the reversible n -bit comparator have been presented. The simulation results of the proposed comparator show that the circuit works correctly and gives significantly better performance than the existing ones. The comparative study shows that, as an example, for a 64-bit comparator, the proposed design achieves the improvement of 24.4% in terms of number of gates, 19.9% in terms of garbage outputs, 7.7% in terms of quantum cost, 25.77% in terms of area and 3.43% in terms of power over the existing best one. Area and power analysis also show that the proposed design is the most compact as well as a low power circuit.