Power efficient optimum design of the Reversible Plessey Logic Block of a field-programmable gate array

Abstract

Reversible logic has captured significant attention in recent time for its reduced power consumption property which is one of the main concerns of digital logic design. Reprogram ability, higher speed, higher density, non-recurring engineering (NRE) costs, massive parallel operations and many other favoring factors have made prominent use of the Field-Programmable Gate Array (FPGA) in today's electronics world. In this paper, the most significant part of an FPGA, the Plessey Logic Block is designed in reversible manner with optimal parameters. On the way to design the proposed reversible Plessey Logic Block, each individual components such as reversible D-Latch, reversible Decoder, reversible Multiplexer, reversible Master-Slave Flip-Flop, reversible RAM are designed separately.. The proposed design of the individual parts is primarily optimized for the number of gates, garbage outputs, quantum cost and delay. In addition, area and power are optimized to ensure the power efficiency of the circuits. Two 4×4 reversible gates, namely HNF (Hafiz-Naz-Flip-Flop) gate and HND (Hafiz-Naz-Decoder) gate, are proposed to achieve the optimization goal. Moreover, proposed algorithms, lemmas and theorems certify the novelty of the proposed design. Compared to previous works, the proposed counter parts of Reversible Plessey Logic Block require less number of gates, garbage outputs, quantum cost and the delay. Finally, the proposed Reversible Plessey (4×2) Logic Block is compared with existing designs. The comparative result proves the efficacy and novelty of the proposed design showing improvement 51.62% in terms of number of transistor, 73.57% in terms of area (mm2) and 34.12% in terms of power (mW) with respect to the corresponding metrics of the best design in literature.