Derivative Superposition Technique Research Articles

A 28 GHz Highly Linear Up-Conversion Mixer for 5G Cellular Communications

In this paper, we present a highly linear direct in-phase/quadrature (I/Q) up-conversion mixer for 5G millimeter-wave applications. To enhance the linearity of the mixer, we propose a complementary derivative superposition technique with pre-distortion. The proposed up-conversion mixer consists of a quadrature generator, LO buffer amplifiers, and an I/Q up-conversion mixer core and achieves an output third-order intercept point of 15.7 dBm and an output 1 dB compression point of 2 dBm at 27.6 GHz, while it consumes 15 mW at a supply voltage of 1 V. The conversion gain is 11.4 dB and the LO leakage and image rejection ratio are −56 dBc and 61 dB, respectively, in the measurement. The proposed I/Q up-conversion mixer is suitable for 5G cellular communication systems.

An Ultra-wideband Low-power Low-noise Amplifier Linearized by Adjusted Derivative Superposition and Feedback Techniques

Ultra-wideband (UWB) applications require low-power and low-noise amplifiers (LNAs) that can operate over a wide frequency range. However, conventional LNAs often suffer from poor linearity and high-power consumption. This research work proposes a novel LNA design that uses the adjusted derivative superposition (DS) technique and feedback to improve the linearity and reduce the power consumption of UWB LNAs. The DS technique enhances the third-order intermodulation (IM3) cancellation by adjusting the bias currents of the transistors, whereas the feedback improves the stability and input matching of the LNA. The LNA is implemented using a degenerated common source topology in a 180 nm standard CMOS technology. The simulation results show that the LNA achieves a power gain of 10–12.2 dB, an input third-order intercept point (IIP3) of about 12 dBm, and a noise figure of less than 2.5 dB over the UWB frequency band of 3.1–10.6 GHz. The input reflection coefficient is less than -10 dB, and the power consumption is 11.6 mW with a 1.5 V power supply. The designed LNA offers a novel and innovative solution for UWB applications that significantly improve the performance and efficiency of UWB LNAs whereas reducing the cost and complexity of implementation.

A Novel High-Linearity Uwb-Lna Based on Post Distortion and Complementary Derivative Superposition Techniques

A Novel High-Linearity Uwb-Lna Based on Post Distortion and Complementary Derivative Superposition Techniques

A two stage cascode LNA using modified derivative superposition technique in [formula omitted] HBT with an IIP3 of 2 dBm and NF of 4.8 dB for IEEE 802.11ad standard

A two stage cascode Low Noise Amplifier (LNA) is designed in 130 nm SiGe HBT. The work focuses on achieving a low Noise Figure (NF), high linearity, and high gain for the LNA in the frequency band of 57.24 GHz-65.88 GHz to be operated in all the four channels of IEEE 802.11ad standard. A modified Derivative SuperPosition technique is used in the first stage of the cascaded LNA to improve the linearity of the circuit. Post layout Electromagnetic (EM) simulation results of the proposed LNA achieves a peak gain of 20.19dB at 59.5GHz, linearity (IIP3) of 2dBm at the maximum gain and also achieved a NF of 4.1dB - 4.8dB in the operating band of frequency. DC power consumption of the proposed circuit is 9.2mW from a supply voltage of 1.2V, with an area occupancy of 311μm×298μm.

Design and Analysis of a Novel 24 GHz Up-Conversion Mixer with Improved Derivative Super-Position Linearizer Technique for 5G Applications.

A 24 GHz high linear, high-gain up-conversion mixer is realized for fifth-generation (5G) applications in the 65 nm CMOS process. The mixer’s linearity is increased by applying an Improved Derivative Super-Position (I-DS) technique cascaded between the mixer’s transconductance and switching stage. The high gain and stability of amplifiers in the transconductance stage of the mixer are achieved using novel tunable capacitive cross-coupled common source (TCC-CS) transistors. Using the I-DS, the third-order non-linear coefficient of current is closed to zero, enhancing the linearity. Additionally, a TCC-CS, which is realized by varactors, neutralizes the gate-to-drain parasitic capacitance (Cgd) of transistors in the transconductance stage of the mixer and contributes to the improvement of the gain and stability of the mixer. The measured 1 dB compression point OP1dB of the designed mixer is 4.1 dBm and IP1dB is 0.67 dBm at 24 GHz. The conversion gain of 4.1 dB at 24 GHz and 3.2 ± 0.9 dB, from 20 to 30 GHz is achieved in the designed mixer. Furthermore, a noise figure of 3.8 dB is noted at 24 GHz. The power consumption of the mixer is 4.9 mW at 1.2 V, while the chip area of the designed mixer is 0.4 mm.

A high linearity low power low-noise amplifier designed for ultra-wide-band receivers

This paper presents a new ultra-wide band (UWB) CMOS low noise amplifier (LNA) with very high linearity and low power consumption for UWB wireless communication applications, where linearity is a big challenge, due to presence of interference and blocker signals, as well as the in-band harmonics of the desired signal components in the lower part of UWB band. The proposed LNA uses a new combination of saturated NMOS and PMOS transistors to improve both of second order and third order nonlinearities, meanwhile improving the noise performance and DC power consumption. In our design two techniques are integrated in a novel approach: Improved Complementary Derivative Superposition (ICDS) technique and Forward Body Bias (FBB) to reduce the threshold voltage of MOSFET, and hence, lowering the DC power. By utilizing a high-pass filter and common source stage in cascode form, wideband impedance matching and optimal noise figure (NF) have been obtained in the proposed UWB–LNA. The Post-layout simulation of the linearized LNA in a 180 nm RF CMOS process shows NF between 2.5 and 4 dB, gain of 10.8 ± 0.5 dB, and S11 less than −10 dB in the entire 3.1–10.6 GHz band. Total DC power consumption is only 6 mW with 1.2 V supply voltage. The average and the maximum of IIP3 in the UWB band are + 3.84 dBm and + 7.27 dBm, respectively, a superior linearity performance compared to the reported UWB ones. The chip area is 926 mm × 1075 mm, including the supply and ESD ring and the pads.

A 0.5 to 6 GHz wideband cascode LNA with enhanced linearity by employing resistive shunt‐shuntfeedback and derivative superposition

AbstractA wideband bipolar low‐noise amplifier (LNA) with enhanced linearity operating in 0.5 to 6 GHz frequency range is proposed in this letter. The LNA design is based on a cascode amplifier with an emitter degeneration RC parallel network and a resistive shunt‐shunt feedback which can improve linearity. The cascode topology in conjunction with the preceding series inductor L is utilized to achieve good wideband input impedance matching, while the wideband output impedance matching is realized by using an emitter follower as a buffer. And the third‐order input intercept point (IIP3) has been improved due to the derivative superposition technique. The wideband LNA presented in this letter was designed and implemented in a JAZZ 0.18 μm SiGe BiCMOS process. The measured results show that from 500 MHz to 6 GHz, the power gain (S21) is 16.5 to 17.1 dB, the noise factor (NF) is 2.7 to 3.3 dB, the current consumption without buffer stage is 12.4 mA at a 3.3 V supply voltage, and the IIP3 is −0.834 dBm at 2 GHz. The chip size is 1.06 × 0.64 mm2.

1.2 V asymmetric-CCC based sub-3 dB NF high IIP3 linearity wideband balun-LNA

A CG-CS wideband balun-LNA using asymmetric capacitive cross-coupling (A-CCC) and an auxiliary current reuse amplifier (ACRA) is reported in the literature. It achieves low noise figure (NF) and high gain at the cost of linearity. To improve the linearity, inductive loads are proposed. However, this is at the cost of increase in chip area. To overcome this problem, a balun-LNA using modified complementary derivative superposition and asymmetric CCC-DS techniques for the ACRA and A-CCC block respectively is proposed in this paper. It dispenses with the inductive loads. The balun-LNAs with and without the proposed linearization are implemented in UMC 180 nm CMOS technology with a supply of 1.2 V and are studied through post-layout simulations. It is found that the proposed LNA has +7.96 dBm increase in average IIP3 compared to the LNA without the proposed linearization. It achieves an average IIP3 of +5.49 dBm with a peak gain of 24.2 dB and minimum NF of 2.18 dB over the bandwidth of 1–3 GHz. The proposed LNA requires an area of 0.3 mm2 and a power of 6.95 mW.

A 45–2500-MHz Push–Pull Driver PA With Cross Coupled and Negative Feedback Technique

Derivative superposition technique (DST) is a common linearization technology for designing driver power amplifier (DPA). However, the performance of DST is sensitive to frequency variation. This letter presents a method to improve the 1-dB bandwidth of the DST. The negative feedback resistance (NFR) and cross-coupled capacitance (CCC) are combined with DST as the core of DPA which is applied to a 45–2500-MHz wireless transmitter. The DPA implements a good performance in the measured 193% relative bandwidth. The linearity is measured with 1-dB compressed output power from 9 to 10.2 dBm and the third-order intermodulation less than −37.23-dBc over the whole frequency band. The overall die area of the PA is 0.044 mm2 at TSMC 180-nm technology process, and it draws 22.8 mA from the 1.8-V supply voltage.

Low power active shunt feedback CMOS low noise amplifier for wideband wireless systems

This paper presents a wideband low-noise amplifier (LNA) based on active shunt feedback to alleviate the trade-off between noise performance and input matching. Low noise and high linearity are achieved by derivative superposition (DS) and complementary derivative superposition (CDS) techniques. Low power is consumed by biasing the transistors in threshold voltage and forward body biasing. With these modified techniques, low noise figure, high linearity, and improved input matching can be attained for 2–8 GHz frequency band. The simulation results of the designed LNA in TSMC RF CMOS 180 nm technology show the maximum power gain of 11 dB with a ripple of ±0.4 dB, noise figure of lower than 3.5 dB over the whole band of 2–8 GHz, maximum IIP2 of +64 dBm and IIP3 of +14 dBm, while dissipating 7 ​mW from a 1.4 ​V supply voltage. It occupies 0.247 ​mm*0.358 ​mm die area.

Design of a Highly Linear Gain Stage with Complementary Derivative Superposition Technique

In this paper a linearization method called complementary common source derivative superposition (CCS DS) is presented. This structure sets both first and second Derivative of transconductance of the stage to the nearly zero values. So it has a very good performance on both 2nd and 3rd order distortion. It is a biasing scheme to cancel second order and third order distortions of the transistors simultaneously. Both NMOS and PMOS transistors of the strucure are bias in the moderade inversion region. To keep amplifying transistors in the region of interest, a CMFB circuit is used. It makes the circuit robust to the process variations. The structure utilizes the current reuse concept and subsequently the stage provides high enough gain without consuming to much power. A brief comparison of common source stages with different derivative superposition (DS) methods is also studied. Based on simulation results, the proposed CCS DS has overall better performance than other DS structures. So this highly linear gain stage could be a part of an LNA, Mixer, or any other RF or IF signal path.

A 0.65 V, linearized cascade UWB LNA by application of modified derivative superposition technique in 130 nm CMOS technology

In this paper, a low-voltage linearized ultra-wideband (UWB) low noise amplifier (LNA) is presented. The core of the proposed circuit is a two-stage cascade structure which is forward body biased to operate under a low supply voltage. In the proposed topology the low linearity drawback of the cascade structure is improved by exploiting the modified derivative superposition (MDS) technique at the second stage. The MDS technique consists of an auxiliary transistor biased in the moderate inversion region paralleled with the main transistor biased in the strong inversion region and two degeneration inductors connected at the source node of the main and auxiliary transistors which altogether aim to cancel out contributions of both the second and third-order non-linearity coefficients on the third-order input intercept point (IIP3). Applying MDS technique on cascade structure has the advantage to have both high linearity and low supply voltage features in an UWB LNA. Simulated at post-layout level in 130 nm RFCMOS TSMC technology, the structure features a 13.8 dBm IIP3, consuming only 11.2 mW from a low supply voltage of 0.65 V. The proposed LNA achieves a relatively flat gain of 12 ± 1 dB, noise figure of 1.8–4 dB, and return power loss less than − 10 dB.

A Wideband High Linearity and Low-Noise CMOS Active Mixer Using the Derivative Superposition and Noise Cancellation Techniques

Using the derivative superposition and noise cancellation techniques, a high linearity, enhanced conversion gain, and low noise figure (NF) CMOS active mixer is presented for wideband applications. The third-order input intercept point (IIP3) of the proposed mixer is improved by cancelling the intrinsic second-order derivative transconductance (g ) of the main transistor. This is achieved by using an auxiliary transistor which is biased in the weak inversion region to create g with the same amplitude and opposite sign relative to the main transistor. A linear path consisting of two parallel transistors is utilized to cancel the thermal noise of the input transistors. A constant transconductance (Gm) bias circuit is employed to achieve robust performance against process, voltage and temperature variations. Detailed analysis of the proposed mixer is presented, and extensive simulation results are provided to evaluate the efficiency of the utilized techniques. The simulated mixer operates from 500 MHz to 3.1 GHz RF input frequency. Post-layout circuit-level simulation results using a 90-nm RF CMOS process with Spectre-RF reveal that the IIP3 and conversion gain of the proposed mixer are improved about 6.1 dB and 6.2 dB, respectively, compared to the conventional CMOS active mixer. Also, the NF of the proposed mixer is decreased about 2 dB. The simulated S11 is less than − 12 dB in whole RF range. It consumes 13.9 mW from a single 1.1 V power supply which is approximately 60% more than that of the conventional active mixer.

A Low Power Impedance Transparent Receiver with Linearity Enhancement Technique for IoT Applications

A low power receiver with impedance transparent RF front end is presented. By using the 4-path passive mixer and the active feedback of LNA, the baseband impedance profile is further transferred to receiver input. While a LO-defined input matching is formed by RF front end, the linearity of entire receiver chain is improved. Furthermore, derivative superposition technique is employed to cancel the distortion of the CMOS LNA. A 3rd-order active-RC filter is designed with current-efficient feedforward compensated OTA. And a digital-to-time converter (DTC) assisted fractional-N all-digital phase-locked loop (ADPLL) is codesigned with receiver to meet the IoT requirements. The presented receiver is fabricated in 55 nm CMOS technology with an active area of 2.3 mm2 and power consumption of 20 mW. Measurement results show that the receiver achieves 5.3 dB NF with 78 dB gain from 0.6 to 1 GHz, the RX out-of-band IIP3 is +8 dBm, and in-band IIP3 is −10 dBm, and the ADPLL achieves −94 dBc/Hz in-band PN and −120.5 dBc/Hz at 1 MHz offset.

A low power fully differential RF receiver front-end for 2.4 GHz wireless sensor networks

In this paper, a novel merged LNA-mixer denoted as LNMA is proposed. The proposed LNMA consisting of a folded cascode LNA using improved derivative superposition technique and folded double-balanced subthreshold mixer using capacitor cross-coupled common-gate transconductor and it is integrated with on-chip LC voltage controlled oscillator (LC-VCO). In LNMA, a diode and power clamp based on-chip ESD protection circuit is used to tolerate ESD current of human-body-model specifications. To evaluate its performance, it is implemented in 0.18-µm MMRF CMOS process with 1-V supply, studied through post layout simulation and compared the results with other reported works. It achieves higher conversion gain of 27 dB, lower noise figure of 9.5 dB, lower input return loss (S11) of − 20 dB, higher third-order input intercept point (IIP3) of – 16 dBm and higher IIP2 of + 29.9 dBm compared to the works reported in the literature. The on-chip oscillator has the lower phase noise of – 114 dBc/Hz. The proposed LNMA and the LC-VCO achieves the power consumptions of 1.6 and 1.72 mW, respectively at 1-V power supply.

Erratum to: A 1-V 2.4 GHz Low-Power CMOS LNA Using Gain-Boosting and Derivative Superposition Techniques for WSN

In the literature, for Zigbee receivers using cascode LNAs, a number of techniques such as gain-boosting, derivative superposition technique and forward body bias have been proposed individually for improving the gain, linearity and reducing the power dissipation of the LNA respectively. In this paper, a cascode LNA which combines all the three techniques is proposed. To study the efficacy of combining the three techniques, the proposed LNA is designed in UMC 0.18-µm standard CMOS process with the supply voltage of 1.0 V and studied through post-layout simulation at 2.4 GHz ISM band. The LNA which combines all the three techniques is found to be superior compared to the LNAs which use only two of the above techniques. This LNA also has better gain (25.63 dB), better linearity (5.8 dBm) and better figure of merits at the cost of marginal increase in the noise figure (2.45 dB) and power dissipation (2.77 mW) compared to the LNAs reported in the literature.

A High-Linearity Wideband Common-Gate LNA With a Differential Active Inductor

A capacitor cross-coupled (CCC) wideband common-gate low-noise amplifier (CGLNA) with improved linearity and frequency response is presented. A novel differential active inductor (AI) is designed to improve the in-band gain flatness and high-frequency gain using the gate-inductive gain-peaking technique. The AI prevents the small-signal current flowing to the ground through the gate–drain capacitors. The CCC technique improves noise performance and saves power. However, it will also increase nonlinear distortions due to the boosted signal amplitude. To overcome the CCC-induced linearity deterioration, the derivative superposition technique is employed by using two parallel input transistors biased at different regions. The measurement results of the fabricated prototype in a 0.18- $\mu\text{m}$ CMOS process show that the voltage gain, the minimum noise figure, and the third-order intercept point are 16.9 dB, 2.5 dB, and 5.5 dBm, respectively, within the 3-dB bandwidth from 100 MHz to 1.45 GHz. The CGLNA consumes 9.3 mW from a 1.8-V supply and the active area is $0.29\times 0.26 \text{mm}^{2}$ .

A 2 GHz 20 dBm IIP3 Low-Power CMOS LNA with Modified DS Linearization Technique

The linearization technique for low noise amplifier (LNA) has been implemented in standard 0.18-㎛ BiCMOS process. The MOS-BJT derivative superposition (MBDS) technique exploits a parallel LC tank in the emitter of bipolar transistor to reduce the second-order non-linear coefficient (g m2 ) which limits the enhancement of linearity performance. Two feedback capacitances are used in parallel with the base-collector and gate-drain capacitances to adjust the phase of third-order non-linear coefficients of bipolar and MOS transistors to improve the linearity characteristics. The MBDS technique is also employed cascode configuration to further reduce the second-order nonlinear coefficient. The proposed LNA exhibits gain of 9.3 ㏈ and noise figure (NF) of 2.3 ㏈ at 2 ㎓. The excellent IIP3 of 20 ㏈m and low-power power consumption of 5.14 ㎽ at the power supply of 1 V are achieved. The input return loss (S 11 ) and output return loss (S 22 ) are kept below -10 ㏈ and -15 ㏈, respectively. The reverse isolation (S 12 ) is better than -50 ㏈.

A CMOS low noise amplifier with employing noise cancellation and modified derivative superposition technique

A wide band resistive feedback CMOS low noise amplifier (LNA) with Modified Derivative Superposition (MDS) technique is designed by using TSMC RF CMOS 0.18μm technology. In this paper, the main NMOS transistor is biased in strong inversion and auxiliary NMOS transistor is biased in the moderate inversion, so third order nonlinear current of two transistors can be canceled out and high third order input intercept point (IIP3) can be attained. In other method, the main NMOS transistor is biased in moderate inversion and an auxiliary PMOS transistor is biased in weak inversion. By this technique, second and third order input intercept point (IIP2 and IIP3) are improved. With common gate transistor in cascode structure and auxiliary transistor, thermal noise of main transistor can be canceled. The linearized LNA demonstrates IIP2 and IIP3 average improvement of +17dB and +18dB with PMOS transistor rather than NMOS transistor in the frequency range of 3.1–10.6GHz. Maximum power gain of 22dB, minimum noise figure (NF) of 2.3dB with a power dissipation of 5.3mW (without buffer) are obtained under a 1.8V power supply in the frequency range of 5–10.6GHz. The chip area is 660µm×748µm.

A high linearity and high gain Folded Cascode LNA for narrowband receiver applications

Folded Cascode (FC) Low Noise Amplifier (LNA) is preferred for low voltage and low power RF applications. A FC LNA with gm-boosting technique is reported in the literature. Under low voltage operation, linearity of the LNAs is degraded due to transconductance and drain conductance nonlinearities. To improve the linearity of the LNAs, several techniques namely Harmonic Termination Network, Derivative Superposition, Modified Derivative Superposition (MDS) techniques are reported in the literature. In this paper to achieve high linearity for the gm-boosting FC LNA, MDS technique is incorporated at the Common Source (CS) stage and is proposed. In order to evaluate the efficacy of this approach, the proposed LNA is designed and implemented in UMC 0.18µm MMRF CMOS process for 2.44GHz. From the simulation results, it is found that the proposed LNA achieves a gain (S21) of 14.6dB, Noise Figure (NF) of 2.9dB, Input matching (S11) of −15dB and third order Input Intercept Point (IIP3) of +4.19dBm. The power consumption of LNA is 3.8mW for a supply voltage of 0.6V. The proposed LNA has a higher Figure of Merit (FoM) than that of other Cascode LNAs reported in the literature.