A 2 GHz 20 dBm IIP3 Low-Power CMOS LNA with Modified DS Linearization Technique

Abstract

The linearization technique for low noise amplifier (LNA) has been implemented in standard 0.18-㎛ BiCMOS process. The MOS-BJT derivative superposition (MBDS) technique exploits a parallel LC tank in the emitter of bipolar transistor to reduce the second-order non-linear coefficient (g m2 ) which limits the enhancement of linearity performance. Two feedback capacitances are used in parallel with the base-collector and gate-drain capacitances to adjust the phase of third-order non-linear coefficients of bipolar and MOS transistors to improve the linearity characteristics. The MBDS technique is also employed cascode configuration to further reduce the second-order nonlinear coefficient. The proposed LNA exhibits gain of 9.3 ㏈ and noise figure (NF) of 2.3 ㏈ at 2 ㎓. The excellent IIP3 of 20 ㏈m and low-power power consumption of 5.14 ㎽ at the power supply of 1 V are achieved. The input return loss (S 11 ) and output return loss (S 22 ) are kept below -10 ㏈ and -15 ㏈, respectively. The reverse isolation (S 12 ) is better than -50 ㏈.