A High linearity CMOS low noise amplifier for 3.66 GHz applications using current-reused topology

Abstract

A narrow band CMOS low noise amplifier (LNA) achieving high third-order input intercept point (IIP3) is proposed exploiting a non-linearity cancelation technique at RF frequency. In the modified derivative superposition (MDS) technique, one transistor is biased in the strong inversion region and the other is biased in the moderate inversion region instead of weak inversion region. A current-reused technique is employed to increase the trans-conductance (gm) of the amplifier and as well as the gain of LNA without increasing the power consumption. The linear LNA was designed and simulated in 0.13μm CMOS process. A gain of 14dB at 3.66GHz was exhibited and the simulated noise figure (NF) was 2dB. An IIP3 of 10.5dBm and a power consumption of 2.4mW from a 0.8V supply voltage were achieved. An input return loss (S11) of −10.6dB and an output return loss (S22) of −27dB were provided.