A CMOS Low Noise Amplifier for 5.6GHz with Employing Current-Reused Topology and Modified Derivative Superposition Technique

Abstract

The design of a highly linear and low noise complementary metal oxide semiconductor (CMOS) low noise amplifier (LNA) for use at 5.6 GHz frequency with an inductive source degeneration circuit is suggested manipulating the modified derivative superposition (MDS) method. In this method NMOS transistors ( M <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and M <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) as the main and auxiliary transistors were biased inside the strong and moderate inversion areas, respectively. A current-reused method is engaged toward growth the transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) of the amplifier in addition to the gain of the LNA, deprived of growing the power dissipation. The linear of LNA was considered and simulated in 0.18 μm CMOS progression. Simulation consequences of LNA exhibit IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> of 12.1dBm with a power gain of 18.6 dB. The input return loss is -14.1 dB and output return loss is -13.7dB in the frequency of 5.6 GHz. Noise figure (NF) of 2.4dB by a power dissipation of 5.2mW are acquired with a 1.8V supply in the frequency of 5.6 GHz. Post-layout simulation consequences obtained the IIP3 of +9.2 dBm and power gain of 16.7 dB. The chip area is 860.43 μm×957.26 μm.