Depletion-mode FET Research Articles

Characterization of RF power BJT and improvement of thermal stability with nonlinear base ballasting

A novel base ballasting scheme for interdigitated power RF bipolar transistors has demonstrated improved performance and thermal stability. The nonlinear ballast resistor in series with each base finger is implemented using a depletion-mode FET, which requires only minor modification in the fabrication process. Mixed-mode simulation, instead of analytical equations, is used for more accurate device characterization.

Integrated enhancement- and depletion-mode FET's in modulation-doped Si/SiGe heterostructures

We present results of enhancement and depletion mode transistors fabricated on the same layer structure of Si/SiGe, without using gate recess. The current in the enhancement mode device is controlled by a p-n junction, while that of the depletion-mode device is controlled by a Schottky barrier. A peak transconductance of 327 mS/mm and 417 mS/mm has been achieved in 0.5-μm gate length depletion and enhancement-mode transistors, respectively.

Applications of ZnO-based glass membranes to mos devices

The characteristics of capacitance and voltage (C-V) curves in P-channel polycrystalline silicon field effect transistors (FETs), passivated by BaF 2 and ZnF 2 containing ZnOB 2O 3SiO 2Al 2O 3P 2O 5 glass with various OH − ion content, were investigated. When the OH − ion absorption coefficients in the glass increased, there was an adverse effect on the hysteresis C-V curve shifts. The content of ZnO replaced by the content of BaF 2 in ZnOB 2O 3SiO 2Al 2O 3P 2O 5 glass, had an affinity for OH − ions. Source-drain current and voltage (I-V) characteristics of both the typical enhancement and depletion mode field effect transistors, passivated and rounded at 750°C by these glass membranes, were confirmed.

Fabrication and characterization of a depletion-mode ZnS/sub 0.07/Se/sub 0.93/ MESFET

We report the fabrication and characterization of a depletion-mode n-channel ZnS/sub 0.07/Se/sub 0.93/ metal-semiconductor field effect transistor (MESFET). A ZnSSe FET could be a key element in opto-electronic integration consisting of light emitters, light receivers and MESFET pre-amplifiers. Mesa isolation, recess etching and self-alignment techniques were adopted to optimize the MESFET performance. Source and drain (S/D) ohmic contacts and gate Schottky contact were formed by Cr/In/Cr and Au deposition, respectively. Depletion mode FET's with varying gate width-to-length ratio of W/L=200 /spl mu/m/20 /spl mu/m, 200 /spl mu/m/4 /spl mu/m and 200 /spl mu/m/2 /spl mu/m were fabricated. A 2 /spl mu/m FET was characterized as follows: the turn-on voltage, V/sub on//spl ap/1.75 V, the pinch-off voltage, V/sub p//spl ap/-13 V, the unit transconductance, g/sub m//spl ap/8.73 mS/mm, and the breakdown voltage with zero gate-source bias, BV/spl ap/28 V.

Application of BaF2-B2O3-GeO2-SiO2 glasses to metal-oxide-silicon field-effect transistors

The capacitance and voltage characteristics of field effect transistors passivated by BaF2-B2O3-GeO2-SiO2 glasses with various water contents were investigated. As the OH absorption coefficients of the glass increased, adverse effects on the recovery of hysteresisC-V curve shifts was seen. The water content is related to the fluoride content of the BaF2−B2O3−GeO2−SiO2 glass. The viscous flow point of the glass was lowered with increasing ionic character obtained from Hannay's equation. The source-drain current and voltage (I-V) characteristics of typical enhancement and depletion mode field effect transistors passivated with these glasses were investigated.

A relationship between interface trap density and transconductance in depletion-mode field effect transistors

A simple relationship between the interface trap densities and transconductance of depletion mode field-effect transistors is derived without any simplifying assumptions regarding the energy distribution of the traps. Using this relationship and the experimental transconductance data, interface trap densities in GaAs and InP were calculated and compared to their values obtained using capacitance versus voltage measurements. Our method provides a simple and efficient technique of estimating interface trap densities based on transconductance data that are readily given in the pertinent literature.

Constant-current circuit-biasing technology for GaAs FET IC

A new constant-current biasing technology has been proposed, analyzed, and applied to GaAs FET IC's using n-channel depletion-mode FET's. Current-mirror (CM) type current-sink (CS) circuits were proposed as a new building-block circuit. The monolithic prototype samples were fabricated, and the CM characteristics were observed experimentally. The CS currents were insensitive to the V/sub th/-variation over 0.4 V, and the temperature coefficient became as small as -0.04%//spl deg/C. Moreover, this circuit was resistant to the sidegating effect. The circuit was successfully applied to a GaAs lightwave communication IC, and good stability against temperature variation was demonstrated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

New RTD-bootstrapped current and voltage references. II. Mirror-based references

For pt.I see ibid., vol.41, no.11, p.740-43, 1994. New current and voltage references are proposed which utilize depletion-mode field effect transistors and resonant tunneling diodes (RTDs) in a negative, inverting current mirror. High-fidelity SPICE simulation of a double-cascode reference implementation suggests that supply rejection is of the same order as that of the best existing all-MESFET references.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

New RTD-boostrapped current and voltage references. I. Self-bootstrapped references

New current and voltage references are proposed which utilize depletion-mode field effect transistors and resonant tunneling diodes (RTDs) in a self-bootstrapped configuration to take advantage of the ultra-low local transconductance of RTDs and the high output-impedance of cascoded amplifier stages. These references promise improved supply rejection compared with that of the best existing GaAs MESFET voltage references. >

Silicon oxide deposited by direct photolysis of N 2O and SiH 4 at 185 nm on sulfur-treated InP: application to InP MISFETs

We report on silicon oxide deposited by direct photolysis at 185 nm of an N 2OSiH 4 mixture. Films are deposited at 250°C under a 665 Pa pressure on indium phosphide (InP). To determine the best insulator in terms of physico-chemical and electrical properties, the ratio R = SiH 4 N 2 O has been varied. A quasi-stoichiometric silicon oxide is obtained for R = 2% (O/Si = 1·87 instead of 2), the hydrogen and the nitrogen contents being, respectively, ≈15% and ≈5%. Electrical characterization has been done on Metal Insulator Semiconductor (MIS) diodes. After dipping InP in an (NH 4) 2S X solution, and after an appropriate annealing procedure, the density of states N ss is of the order of 10 11 eV −1 cm −2. A quite good resistivity of 10 15 ohm.cm is observed. Simple depletion mode Field Effect Transistors (MISFETs) are then made, and present a transconductance g m of 63 mS/mm and an F max of 20 GHz.

Characteristics of in-situ deposited Si 3N 4⧸Si⧸In 0.53Ga 0.47As metal-insulator-semiconductor structures

Interfacial properties of Si 3N 4/Si/InGaAs metal-insulator-semiconductor structures are studied in detail. Both the Si 3N 4 and Si layers are deposited in-situ in an ultrahigh vacuum chemical vapor deposition chamber on as-grown MBE In 0.53Ga 0.47As surfaces. In-situ deposition is found to be crucial to obtain low interface-trap density. By incorporating a pseudomorphic Si interlayer up to 4 monolayers, it is shown that frequency dispersion of CV curves reduces as the thickness of the Si layer increases. A minimum frequency dispersion is obtained, which is the same as that of the Si 3N/(bulk Si) interface, when the thickness of the Si is 3 to 4 monolayers. In a recent paper, we have shown that the frequency dispersion is due to tunneling related trapping. The present results, therefore, indicate that the density of tunneling related traps is reduced as the thickness of the Si interlayer increases. In this paper, the conductance and quasi-static CV methods are also used to characterize the interface trap density. The minimum interface trap density of these samples is found to be of the order of low 10 11 eV -1 cm -2 depending on the deposition conditions. Dependence of the interface trap density on the deposition temperature will also be reported. Metal-insulator-semiconductor depletion-mode field effect transistors fabricated on in-situ deposited samples exhibit a maximum transconductance of over 200 mS/mm for devices with 2.2 μm gate length.

TEMPERATURE MODELING OF GaAs DCFL

Direct-Coupled FET Logic (DCFL) is an important logic family for LSI GaAs FET circuits because of its simple structure and good speed/power performance. Since it is especially sensitive to temperature shifts of performance, accurate temperature modeling is critical for design of DCFL circuits. Using a version of SPICE modified to include FET temperature dependence, the performance of DCFL is simulated over temperature and compared with measured results. In addition, an improved version of DCFL known as E-E Logic (Enhancement-Enhancement Logic) is modeled over temperature. The performance of E-E Logic is compared to DCFL with depletion-mode FET and saturated resistor loads over temperature. E-E Logic is found to offer improved yield, power dissipation and performance control compared to conventional DCFL.

A microdielectric analysis of moisture diffusion in thin epoxy/amine films of varying cure state and mix ratio

AbstractRecent work has shown that moisture diffusion coefficients can be measured in thin polymer films through monitoring changes in permittivity with microdielectric sensors. The sensor is constructed in silicon and consists of an interdigitated electrode and two depletion mode field effect transistors. When operated in conjunction with appropriate external circuitry, the sensor measures dielectric constant and loss factor of any material placed on the SiO2 insulator and aluminum electrodes. The dielectric properties are measured locally within the first 10 microns of the film in contact with the sensor. As a thin polymer film on the sensor is exposed to a high relative humidity, the dynamically measured dielectric constant can be used to determine exactly when the moisture arrives at the polymer‐SiO2 interface and the rate at which the concentration increases. The magnitude of the change in permittivity after equilibration has also been related to total amount of moisture uptake. In this investigation, several epoxy/amine films of varying mix ratios and cure state are cured on microdielectric sensors. The films, approximately 100 microns thick, are alternately exposed to wet and dry environments. Diffusion coefficients for both absorption and desorption are determined from the dielectric data as a function of cure state and epoxy/amine mix ratio. In addition, relative changes in amount of moisture uptake after equilibration is monitored.

GaAs field-effect transistor with an atomically precise ultrashort gate

We present a new type of depletion-mode field-effect transistor (FET) with an inherently ultrashort gate length. The device is fabricated exclusively via molecular beam epitaxy (MBE) in GaAs/AlGaAs by cleaved-edge overgrowth of a suitably prepared MBE-grown substrate. The channel, as well as the gate, of this T-FET consists of a high-mobility, two-dimensional electron gas (2DEG) generated by modulation doping of GaAs quantum wells. The planes of the 2D systems are orthogonal to one another forming a ‘‘T’’ whose legs approach each other at the intercept to within 200 Å. In this way, the thickness of one of the quantum wells (200 Å) established the gate length of the device. All elements of the T-FET are completely immersed into the semiconductor material and all relevant length scales are established to atomic precision by MBE. Schottky barriers do not enter the device characteristics. Our first T-FET reaches transconductances of 196 and 410 mS/mm at 77 and 4.2 K, respectively.

GaAs trickle transistor dynamic logic

A GaAs dynamic logic gate is proposed which uses a trickle transistor to compensate for leakage from the precharged node. This trickle transistor dynamic logic (TTDL) circuit is configured as a domino logic gate and a differential cascode voltage switch logic (CVSL) gate. Delay chains were implemented in a 1- mu m GaAs enhancement/depletion (E/D) process where the depletion-mode FETs (DFETs) and the enhancement-mode FETs (EFETs) have threshold voltages of -0.6 and 0.15 V, respectively, in order to obtain an experimental characterization of these gates. In addition, the TTDL gates were used to implement a 4-b carry-lookahead adder. The adder has a critical delay of 0.8 ns and a power dissipation of 130 mW. >

Pseudomorphic ZnSe/n-GaAs doped-channel field-effect transistors by interrupted molecular beam epitaxy

The fabrication and current-voltage characteristics of the first depletion-mode field-effect transistors based on a pseudomorphic ZnSe/n-GaAs heterointerface are described. The devices are doped-channel field-effect transistors produced by means of interrupted growth with the use of two separate molecular beam epitaxy systems. Very strong (visible to the naked eye) reflection high-energy electron diffraction intensity oscillations persist for 120 periods when ZnSe is nucleated on the GaAs epilayer. The current-voltage characteristics of the transistors are close to ideal; channel modulation indicates that the Fermi level is not pinned at the ZnSe/GaAs interface.

Characterization of beam-recrystallized Si films and their Si/SiO2 interfaces in silicon-on-insulator structures: The very thin Si film case

A depletion-mode field-effect transistor is used to determine the electrical characteristics of a silicon-on-insulator (SOI) structure such as the Si film doping, the fixed oxide charges, and the interface trapped charges at the Si/SiO2 interfaces. We consider the case of a very thin Si film, i.e., the Si film thickness is smaller than the maximum depletion layer width. The electrical parameters of the SOI structure are derived from drain-source current versus gate voltage and transconductance characteristics, provided that the back Si surface is accumulated by a proper substrate biasing. The device can be of small dimensions and can be used in process control without any extra process step.

Comparison of field-effect transistor logic families for a GaAs depletion-mode metal semiconductor field-effect transistor

Normally-on or depletion-mode field-effect transistors (MESFET) form the basis of the most mature and robust GaAs active-circuit technology. Because of the negative threshold voltage, depletion-mode metal semiconductor field-effect transistors (D-MEFSET) need level shifters to enable the output of one transistor to switch the input of the next. Buffered FET logic (BFL) is the most popular approach leading to gates that are fast and have good output-drive capability, but they occupy a lot of space and consume a lot of power. Capacitor – FET logic (CFL) has about one quarter of the power dissipation of BFL and occupies a similar area of GaAs. CFL is as fast as BFL, but the output-drive capability is inferior.The aim of the work described here is to develop a family of CFL gates that are at least as fast as BFL under all loading conditions while maintaining the power advantage of CFL. Bootstrapping the load increases the speed, but the output drive remains unsatisfactory. A super-buffered arrangement results in the lowest power and good output drive but with a slight reduction in speed compared to BFL. A combination of super buffering and load bootstrapping results in a design that meets all requirements. For example, a CFL gate with 12 mW dissipation gives a delay of 49 ps for a fan-out of unity and a loading factor of 13 ps per fan-out. This is compared with the BFL values of 60 ps with 12 ps per fan-out and 40 mW for a gate with comparable area and input capacitance.The super CFL gates have been used in the design of a 2.4 Gb∙s−1 4: 1 multiplexer, which has been successfully fabricated using a standard depletion-mode foundry process. The total power is approximately two thirds of that which would have been dissipated by a BFL realization.

WSi0.11 Schottky gates for GaAs metal semiconductor field-effect transistors

Schottky gates for self-aligned GaAs metal semiconductor field-effect transistors (MESFETs) have been formed by dc magnetron sputtering of WSi0.11 onto sputter-cleaned GaAs surfaces. The WSi0.11/GaAs diodes showed good current-voltage and capacitance-voltage characteristics after annealing at 800 °C. Schottky barrier heights measured by current-voltage were φI-VB ≂0.73 eV with an ideality factor n≂1.14 for large diodes and φI-VB ≂0.67 eV with n≂1.3 for 1×10 μm gates without a self-aligned n+ implant. The n+ self-aligned implant was found to cause leakage current, which was interpreted as a parallel small-area, low-barrier diode at the gate edge. FETs formed with this gate material showed good threshold voltage uniformity with a standard deviation as low as 31 mV for 1 μm enhancement-mode FETs and 49 mV for 1 μm depletion-mode FETs on a 51-mm wafer.

Monolithic integration of a planar embedded InGaAs p-i-n detector with InP depletion-mode FET's

We report the operation of a fully integrated p-i-n FET circuit based on a planar embedded In <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</inf> Ga <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</inf> As p-i-n detector and load resistor with InP depletion-mode FET's. The structure employs selective growth of InGaAs on a semi-insulating InP substrate and selective ion implantation of Si and Be into the InP and InGaAs, respectively. For a 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9</sup> bit error rate at 1.54 m, the circuit achieves a sensitivity of -34 dBm at 90 Mbit/s and -29.5 dBm at 295 Mbit/s.