Abstract
We report the operation of a fully integrated p-i-n FET circuit based on a planar embedded In <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</inf> Ga <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</inf> As p-i-n detector and load resistor with InP depletion-mode FET's. The structure employs selective growth of InGaAs on a semi-insulating InP substrate and selective ion implantation of Si and Be into the InP and InGaAs, respectively. For a 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9</sup> bit error rate at 1.54 m, the circuit achieves a sensitivity of -34 dBm at 90 Mbit/s and -29.5 dBm at 295 Mbit/s.
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