Comparison of field-effect transistor logic families for a GaAs depletion-mode metal semiconductor field-effect transistor

Abstract

Normally-on or depletion-mode field-effect transistors (MESFET) form the basis of the most mature and robust GaAs active-circuit technology. Because of the negative threshold voltage, depletion-mode metal semiconductor field-effect transistors (D-MEFSET) need level shifters to enable the output of one transistor to switch the input of the next. Buffered FET logic (BFL) is the most popular approach leading to gates that are fast and have good output-drive capability, but they occupy a lot of space and consume a lot of power. Capacitor – FET logic (CFL) has about one quarter of the power dissipation of BFL and occupies a similar area of GaAs. CFL is as fast as BFL, but the output-drive capability is inferior.The aim of the work described here is to develop a family of CFL gates that are at least as fast as BFL under all loading conditions while maintaining the power advantage of CFL. Bootstrapping the load increases the speed, but the output drive remains unsatisfactory. A super-buffered arrangement results in the lowest power and good output drive but with a slight reduction in speed compared to BFL. A combination of super buffering and load bootstrapping results in a design that meets all requirements. For example, a CFL gate with 12 mW dissipation gives a delay of 49 ps for a fan-out of unity and a loading factor of 13 ps per fan-out. This is compared with the BFL values of 60 ps with 12 ps per fan-out and 40 mW for a gate with comparable area and input capacitance.The super CFL gates have been used in the design of a 2.4 Gb∙s−1 4: 1 multiplexer, which has been successfully fabricated using a standard depletion-mode foundry process. The total power is approximately two thirds of that which would have been dissipated by a BFL realization.