Slow State Density Research Articles

Investigation of grown ZnS film on HgCdTe substrate for passivation of infrared photodetector

Zinc sulfide (ZnS) thin films were developed on the mercury cadmium telluride (HgCdTe) substrate using the thermal evaporation technique and investigated with X-ray diffraction, energy dispersive analysis of X-rays, atomic force microscopy (AFM) and capacitance-voltage (C-V). The obtained results confirm that the films have a cubic zinc-blend structure with (111) preferred orientation and nearly stoichiometric composition. The AFM measurement reveals that the film is uniform, densely packed and has a smooth surface or very low roughness. The C-V measurement of a ZnS/HgCdTe based metal-insulator-semiconductor device provides the utility of ZnS thin film as a passivation layer for the HgCdTe substrate. The evaluated fixed-charge density, slow state density and fast state density of the device are 4.98 × 1010 cm−2, 4.22 × 1010 cm−2 and 5.32 × 1011 cm−2 eV−1, respectively. Thus, the grown ZnS thin film could be used as a suitable passivation agent in HgCdTe-based infrared detector fabrication.

Electrical properties of plasma-free ultra-low-temperature ALD ZnS passivation on p-type HgCdTe

ZnS thin films have been successfully deposited using metal organic compound with ultra-low-temperature atomic layer deposition (ULT-ALD) at 80 °C. This plasma-free ULT-ALD eliminates the damage to the HgCdTe surfaces due to plasma and high temperature. The capacitance–voltage characteristics of metal–insulator–semiconductor (MIS) structures based on HgCdTe with traditional CdTe/ZnS and ULT-ALD ZnS passivation are studied. The fixed charge surface density at the interface of MIS structures passivated by ALD ZnS was −6.40 × 1011 cm−2, Lower than the value of double-layer passivation 4.20 × 1012 cm−2, and the density of slow states is 5.94 × 1011 cm−3 and 2.61 × 1012 cm−3 respectively. The hysteresis of the MIS structure with ALD ZnS passivation is almost unchanged with temperature. From these findings, combined with characteristics of high density and conformality of ALD films, we conclude that ALD ZnS has better electrical properties than traditional double layer passivation provides significantly improved interface quality, but obtained density of fixed charge is still quite high and should be further reduced.

Investigation of the Effect of Thermal Annealing on the Electrical Properties of the Near-Surface Layer of MBE n-HgCdTe Using MIS Techniques

Heteroepitaxial n-Hg0.78Cd0.22Te films with near-surface graded-gap layers were grown by molecular beam epitaxy and subjected to two-stage thermal annealing in saturated mercury vapor atmosphere. The first stage of annealing was carried out for 2 h at a temperature of 360°C. The second stage was carried out at a temperature of 220°C for 24 h. Similar annealing was carried out after As+ ion implantation to activate the introduced impurity and anneal radiation defects. Based on as-grown and annealed films, metal–insulator–semiconductor (MIS) structures were formed by depositing an Al2O3 dielectric by plasma atomic layer deposition. The admittance of fabricated MIS structures was studied in a wide range of frequencies and temperatures. It was found that after thermal annealing, the properties of the n-HgCdTe surface layer are noticeably changed, which is manifested as a decrease in the density of slow states in the transition layer between the dielectric and the semiconductor, and an increase in the generation of minority charge carriers in the n-HgCdTe near-surface layer. These changes in the properties of n-HgCdTe after thermal annealing are associated with the modification of the defect system of the near-surface layer of the semiconductor and the transition layer between dielectric and semiconductor. No significant changes were detected in the bulk properties of the epitaxial film after thermal annealing. A decrease in the density of states near the interface between HgCdTe and Al2O3 during thermal annealing makes it possible to facilitate the electrical characterization of MIS structures by suppressing hysteresis phenomena.

Improvement of electrical properties of ZnS/CdTe-HgCdTe interface by (NH4)2S treatment

Effect of 20% aqueous ammonium sulphide treatment on electrical properties of ZnS/CdTe-HgCdTe interface was studied by using high frequency capacitance-voltage (C-V) measurements showing significant improvement in surface conditions. MIS structures were fabricated on passivated HgCdTe wafers and C-V measurements were carried out. C-V curves were analysed to evaluate fast interface state distribution with energy, slow state density and fixed charged density. For the sake of comparison two HgCdTe samples were prepared under similar conditions, one was given (NH4)2S treatment after standard surface preparation by I-KI polishing and the other was untreated to act as the base sample. CdTe and ZnS layers were deposited on both the samples, A and B. It was observed that C-V characteristics of (NH4)2S treated sample show significant improvement in comparison to that of untreated sample. Fixed charge density and fast interface charge (fast and slow) density were estimated for both the samples. Average fixed charge density for sample treated with (NH4)2S (4.2 × 1010 cm−2) is reduced by a factor of ~6 compared to untreated sample (2.53 × 1011 cm−2), Average fast interface trap density for sample exposed to (NH4)2S treatment (~3.5 × 1011 cm−2eV−1) improved by a factor of ~3.5compared to untreated sample (~1.3 × 1012 cm−2eV−1) while average slow interface traps estimated for sample treated with (NH4)2S (~3.09 × 1010 cm−2) reduced by ~1.3times than that for untreated sample (~4.1 × 1010 cm−2). Surface and interface stability of the grown sulphide is also studied by repeated ellipsometry and C-V measurements respectively. It is found that it is important to deposit CdTe/ZnS passivation layers immediately after 20% aqueous ammonium sulphide treatment to achieve stable performance. Stability of (NH4)2S treatment with time was also investigated. C-V measurements after approximately 2 months showed improvement in interface properties.

Robustness of Sn precipitation during thermal oxidation of Ge1−xSnx on Ge(001)

The thermal robustness of Sn segregation and precipitation in epitaxial Ge1−xSnx layers on Ge(001) substrates with a Sn content greater than the equilibrium solubility limit has been investigated for applications of Ge1−xSnx in high-performance metal–oxide–semiconductor field-effect transistors (MOSFETs). Sn segregation and precipitation occur on the Ge1−xSnx surface after epitaxial growth of the Ge1−xSnx layer at 150 °C. After the thermal oxidation of the Ge1−xSnx layer below 500 °C, there are no significant decreases in the average Sn content in the Ge1−xSnx layer and no additional Sn segregation on the Ge1−xSnx surface. However, Sn precipitation occurs at the Ge1−xSnx surface during the thermal oxidation of the Ge1−xSnx layer with an average Sn content as high as 8.7% at 600 °C, causing a decrease in the Sn content in the Ge1−xSnx layer. The Sn content in the Ge1−xSnx oxide is 1.5 times greater than that observed near the Ge1−xSnx surface for the sample with a Sn content of 8.7% after the thermal oxidation at 400 to 500 °C. The capacitance–voltage characteristics of the Al/Al2O3/Ge1−xSnx/Ge MOS capacitors treated with thermal oxidation at 400 °C indicate that the slow state density increases with the Sn content. Meanwhile, the small interface state density could be achieved via thermal oxidation of the Ge1−xSnx layer, even with a high Sn content.

The effect of ammonium sulfide treatment on interfacial properties in ZnS/HgCdTe heterostructure

The semiconductor-passivating layer interface, as well as the dielectric properties of the passivants, plays an important role in HgCdTe based photodiodes. ZnS is a commonly uses surface passivant for HgCdTe. The effects of sulfidation on the HgCdTe surface and interfacial characteristics of metal/ZnS/HgCdTe structures are studied. The ZnS layer was deposited by thermal evaporation after sulfidation of HgCdTe substrates. The interfacial properties of the metal insulator semiconductor (MIS) structures were determined by capacitance-voltage (C-V) measurements. A comparison of an untreated and a sulfide treated MIS capacitor showed that the fixed charge density and slow state density were 2 and 7 times lower in the sulfide treated specimens than in the untreated specimens. Sulfidation results in a decrease in the concentration of contaminants originating from the native oxide-covered HgCdTe substrates. This reduction may be due to the formation of S-S or II-S bonds at the surface layer. These bonds might act as barriers against native oxide formation when (NH4)2Sx treated HgCdTe substrates are exposed to air.

Ammonium sulfide treatment of HgCdTe substrate and its effects on electrical properties of ZnS/HgCdTe heterostructure

The semiconductor–passivating layer interface, as well as the dielectric properties of the passivants, plays an important role in HgCdTe based photodiodes. ZnS is a commonly used surface passivant for HgCdTe. This study examined the effects of sulfidation on the HgCdTe surface and interfacial characteristics of metal/ZnS/HgCdTe structures. The ZnS layer was deposited by thermal evaporation after sulfidation. The interfacial properties of the metal insulator semiconductor (MIS) structures were determined. A comparison of an untreated capacitor and a sulfide treated MIS capacitor showed that the fixed charge density (untreated 6.37×10 11, treated 3.2×10 11 cm −2) and slow state density (untreated 5.5×10 11, treated 7.5×10 10 cm −2) were 2 and 7 times lower in the treated than in the untreated specimens. Sulfidation results in a decrease in the concentration of contaminants originating from the native oxide-covered HgCdTe substrates. This reduction may be due to the formation of S–S or II–S bonds at the surface layer. These bonds might act as barriers against native oxide formation when (NH 4) 2S x-treated HgCdTe substrates are exposed to air.

A study of noise in surface and buried channel SiGe MOSFETs with gate oxide grown by low temperature plasma anodization

A study is made of noise in p- and n-channel transistors incorporating SiGe surface and buried channels, over the frequency range f=1 Hz–100 kHz. The gate oxide is grown by low temperature plasma oxidation. Surface n-channel devices are found to exhibit two noise components namely 1/ f and generation–recombination (GR) noise. It is shown that the 1/ f noise component is due to fluctuations of charge in slow oxide traps whilst bulk centers located in a thin layer of the semiconductor close to the channel, give rise to the GR noise component. The analysis of the noise data gives values for the density D ot of the oxide traps in the SiGe and Si nMOSFETs of the order 1.8×10 12 and 2.5×10 10 cm −2 (eV) −1, respectively. The density D GR of the bulk GR centres is equal to 3×10 10 cm −2 in both the SiGe and Si devices. The electron and hole capture cross-sections for these centres as well as their energy level and their depth below the oxide/semiconductor interface are also the same in the devices of both types. This suggests that those GR centers are of the same nature in all devices studied. p-Channel devices show different behaviour with only a 1/ f noise component apparent in the data over the same frequency range. Buried SiGe channel and Si control devices exhibit quite low and similar slow state densities of the order low to mid 10 10 cm −2 (eV) −1 whereas surface p-channel devices show even higher slow state densities than n-channel counterparts. The Hooge noise characterized by the Hooge coefficient α H=2×10 −5 is also detected in some buried p-channel SiGe devices.

Validation of the voltage step technique for determination of slow state density in MOS gate oxides

Presented here is a technique for profiling near interfacial oxide traps based on the McWhorter tunneling model. The technique is verified by comparing slow state densities obtained using the Gp/ω conductance technique, which is an established method for slow state density determination.

Effect of post oxidation processing on dry oxides on n-type 4HSiC

We report a study of the effect of post oxidation processing on the interface quality of dry oxides on n-type 4H SiC. We have found that the processing required to make a polysilicon gated SiC capacitor with full ohmic back contact did not affect the interface state density of the oxide, but rather improved the fixed oxide charge and slow state density, with both effects increasing the further through the process the oxides were taken.

Fast and slow interface state distributions on (100) and (111) Si:SiO 2 surfaces following negative bias stress

The distribution of fast and slow interface states through the silicon bandgap has been measured for the (100) and (111) Si:SiO 2 surfaces. The measurements were carried out before and after damage to the interface using negative bias stress. The results show that both fast and slow states are more easily created on the (111) surface. The shape of the distribution through the gap is similar for both surfaces with the slow state density rising strongly towards the conduction band edge.

Metal-insulator-semiconductor structures of InSb/SiO 2 with very lowinterface trap density

MIS structures fabricated using InSb and silicon dioxide with an interface trap density as low as 4 ×1010 cm-2eV-1 have been achieved. This is about one order of magnitude less than any other reported figure for the InSb MIS system. Both capacitance/voltage and conductance techniques have been employed to study the interface properties of InSb/SiO2. A slow state density of < 1010 cm-2 was observed and the dielectric breakdown field of the oxide was greater than 4 mVcm-1.

Charge exchange mechanisms of slow states in Si/SiO 2

A technique was developed to measure the energy distribution of the density of slow states. From the results we conclude that slow states, related to defects in the SiO 2, exchange their charge directly with the silicon valence band states or indirectly via fast VUV radiation- induced interface states above midgap. Tunnelling via fast interface states below midgap or via conduction band states was not observed.

Influence of the surface treatments by multipolar plasma on the slow state tunnel kinetics at the In0.53Ga0.47As/Si3N4 interfaces

In this work a study of the capture and emission kinetics related to the slow interface states present in In0.53Ga0.47As/Si3N4 interfaces on MIS (metal-insulator-semiconductor) structures is reported. These states are found to be filled by electrons from the semiconductor conduction band by means of a tunnel mechanism. On the other hand, charge tunnel emission from the slow states takes place through the fast interface states energetically located in the semiconductor bandgap. The influence of surface plasma treatments on the slow state kinetics has been analyzed. The results indicate a different nature and electrical behaviour of the slow interface states when they are located in the native oxide layer or in the silicon nitride. The surface treatments allow us to eliminate completely the slow states related to the native oxide and to reduce significantly the density of slow states in the silicon nitride.

Vacuum ultraviolet radiation damage in electron cyclotron resonance and reactive ion etch plasmas

A comparative study of vacuum ultraviolet radiation damage has been carried out in an electron cyclotron resonance (ECR) and reactive ion etching (RIE) hybrid chamber. The damage was measured by changes in the density of interface states, the midgap capacitance–voltage shifts, and from photo I–V gate voltage shifts in metal–oxide semiconductor (MOS) capacitors before and after plasma exposure. The results suggest that the damage found in the samples exposed to either ECR or RIE plasmas appears in the form of neutral electron traps in the bulk of the SiO2 film and ‘‘slow’’ interface states. The positive charge found in the exposed samples results from the filling and emptying of these slow interface states and not from trapped holes. Electron trap densities are found to be in the low to mid 1012 cm−2 range for all plasma-exposed samples. Even after a standard post-metalization anneal (PMA), the density of electron traps is only reduced by approximately a factor of 2 and appears relatively independent of the type of the plasma exposure. The density of the slow interface states is found to be in the high 1011 cm−2 range and in the low 1010 cm−2 range, for the ECR plasma samples, before and after the PMA, respectively. The RIE exposed slow state density was initially ≂2×1012 cm−2 and reduced to 2×1111 cm−2 after the PMA, an order of magnitude higher than that of the ECR-plasma exposed samples.

High-performance metal/SiO2/InSb capacitor fabricated by photoenhanced chemical vapor deposition

The high-performance AuCr/SiO2/InSb metal-oxide-semiconductor capacitor was fabricated successfully using photoenhanced chemical vapor deposition. The 1200-Å-thick SiO2 layer was deposited on the InSb substrate at a temperature below 200 °C. Their electrical and structural properties were analyzed by capacitance-voltage and Auger electron spectroscopy, respectively. The capacitance-voltage results show that the optimal growth temperature of SiO2 is 150 °C at which the flat-band voltage of the capacitor is close to ideal and the slow interface state density is less than 5 × 1010 cm−2. For SiO2 deposited at a lower temperature, although the flat-band voltage and interface state are poorer, the subsequent thermal annealing at 150 °C for 12 h improves both quantities to the level as the optimal condition. However, for SiO2 deposited at a higher temperature (190 °C), the flat-band voltage shifts to −4 V and the slow state density increases to 1.1 × 1011 cm−2. It is found from the Auger depth profile that whatever the deposition temperature was a Si-rich region followed by an oxygen-rich region was formed at the SiO2/InSb interface. These observations are shown to be consistent with the electrical characteristics of the capacitor.

Fast and slow states at the interface of amorphous silicon and silicon nitride

The effects of a graded composition layer at the amorphous silicon/nitride interface are studied using transient photoconductivity. The graded layer causes a large increase in the density of slow states (electrons trapped within the nitride), but does not influence the fast interface states. The kinetics of trapping and release are measured and a model of field assisted hopping and thermal excitation is proposed. The different origins of slow and fast states are also discussed.

The Origin of Slow States at the Interface of a-Si:H and Silicon Nitride

ABSTRACTTransient photoconductivity is used to investigate the origin of slow states near the interface of a-Si:H and silicon nitride. A graded composition of the nitride layer near the interface greatly increases the density of slow states. We deduce that slow states are bulk nitride traps and that the magnitude of charge storage is largely determined by the composition dependence of the localization radius of electrons within these traps. The kinetics of charge storage and release are found to be very different and are interpreted in terms of an activation step at the interface.

Single- and double-layer insulator metal-oxide-semiconductor capacitors on indium arsenide

Single- and double-layer insulator MOS capacitors on InAs were investigated for possible MOS device applications. The single layers were formed by anodic oxidation or by reactive evaporation of SiO 2. The double layers were formed by depositing SiO 2 on the anodic oxide. With the anodically oxidized InAs, the fast state and fixed charge densities were respectively two and five time greater than with the deposited SiO 2. The slow state densities were approximately the same for these insulators. No collected charge between the two insulators of the double-layer capacitors was observed.

Direct observation of charge storage in the surface states of germanium and silicon

The stored charge in the surface states of germanium and silicon crystals, held in an ambient of wet oxygen, has been measured directly, using a glass fibre probe and a high impedance electrometer. The charge is attributed to layers of adsorbed water molecules, and the voltage across the dipole layer has been deduced from the distribution of potentials in the system and the values of the work functions of the electrodes. The density of slow states provided by these data is approximately 5 × 1014 cm-2 for both germanium and silicon, suggesting that Tamm states may be of practical significance at the oxide surfaces. Decay curves of the surface charge in both wet and dry ambients provide evidence for an electron transfer process through the oxide, and the oscillatory behaviour of the charge following a disturbance of the field suggests the presence of a heterogeneous distribution of slow states throughout the bulk of the oxide layer. Relaxation times of 300 to 500 seconds for the slow states were obtained.