Interface Trap Density Research Articles

Vertical GeSn/Ge Heterostructure Gate-All-Around Nanowire p-MOSFETs

In recent years, Ge-based group-IV alloys (GeSn, SiGeSn) have received a significant amount of attention as candidates to replace Silicon for future low power and high performance nanoelectronics [1]. The interest in these materials stems primarily from the fact that, by varying the Sn-content of the alloy, it is possible to precisely tune its bandgap from indirect to direct [2], which even opens up the possibility to switch the carrier transport from larger mass low mobility L-valley electrons to the lower mass and high mobility Γ-valley electrons. Adding Si atoms into GeSn alloys enables additional strain engineering by decoupling the lattice constant from the band gap and enables the fabrication of devices to target specific applications. Ge exhibits superior hole mobility over Si and GeSn is predicted to further improve carrier mobilities for both electrons and holes, while still retaining Si CMOS compatibility [3]. In this , we present the fabrication and characterization of Ge- and GeSn-based vertical gate-all-around (GAA) nanowire (NW) p-MOSFETs. Multilayer stacks of Ge and GeSn were grown on a Ge virtual substrate (Ge-VS) using industrial CVD reactors and subsequently characterized, confirming the high quality of the alloys.On these GeSn/Ge heterostructures, vertical GAA nanowire FETs were fabricated using a top-down approach. First, nanowires were defined by electron-beam lithography and subsequently etched anisotropically using reactive ion etching (RIE). The diameter of the nanowires was reduced by digital etching, consisting of repeated combined GeOx layer formation by plasma oxidation and removal in diluted HF solution. This way nanowires with a diameter down to 20 nm and a height of 210 nm were fabricated. A two-step process was employed for gate dielectric formation to ensure a low interface trap density: (i), deposition of a thin layer of Al2O3, followed by an O2-plasma post-oxidation step; (ii) deposition of a HfO2 dielectric layer to reach the required EOT (equivalent oxide thickness). TiN deposited by sputtering forms the gate metal. Planarization and isotropic dry etching were performed to remove the TiN on the top of the nanowire. After a second planarization step, NiGe-contacts were formed on the exposed top nanowire by Ni-deposition followed by a forming-gas annealing step. Finally, metal contacts for gate and source/drain were added.The resulting Ge-NW-pMOSFETs exhibit high electrical performances. A low subthreshold slope (SS) of 66 mV/dec, a low drain-induced barrier lowering (DIBL) of 35 mV/V and an I on/I off-ratio of 2.1×106 were measured for nanowires with a diameter of 20 nm. For 65 nm NWs, the I on/I off-ratio improves, which is attributed to the decreased contact resistance on top of the NWs, leading to larger on-currents. The peak transconductance for the Ge NWs reached ~190 µS/µm (V DS=-0.5 V). Adopting a GeSn/Ge-heterostructure, with GeSn on top of the nanowire used as source the device performances are strongly enhanced. The on-current I on was increased by ~32%, mostly due to the reduced contact resistivity of the smaller bandgap of GeSn compared to Ge. It was also observed that adopting GeSn alloys leads to an increase in transconductance, G max, to a respectable value of ~870 µS/µm, almost 3 times larger as reported to date for Ge NWs. Moreover, both SS and DIBL are improved by decreasing the NW diameter as a consequence of improved electrostatic gate control over the channel.These results demonstrate that the incorporation of GeSn into Ge-MOSFET technology yields a significant advantage and confirm its high potential for low-power-high-performance nanoelectronics.Fig. 1: (a) Schematic of the GAA nanowire FET based on a GeSn/Ge-heterostructure. (b) Optical image on the metallic contacts (c) Transfer curve of a Ge nanowire pFET with a diameter of 20 nm. The SS is 68 mV/dec and the DIBL is 35 mV/V. (d) Transfer curves of Ge0.92Sn0.08/Ge nanowire pFETs with a diameter of 65 nm and different EOTs. Acknowledgments The authors acknowledge support from the German BMBF project “SiGeSn NanoFETs”.

(Invited) Thin Epitaxial Single-Crystal Si on Sige Followed By in-Situ Deposition of High-k Dielectrics – Novel Gate Stacks for Achieving Extremely Low Dit and Highly Reliable SiGe MOS

Silicon-germanium (SiGe) is replacing silicon (Si) as the channel layer for the p-type metal-oxide-semiconductor (pMOS) in the aggressively scaled complementary MOS (CMOS) technology. Many research efforts involving SiGe gate stacks have resulted in the attainment of low interfacial trap densities (Dits). Si-passivated SiGe gate stacks are the most promising method to achieve both low Dit and high device reliability. However, regardless of the growth methods, most publications reported the pileup of Ge atoms on top of the grown Si even after extensive treatments. The subsequent process in forming gate stacks, including oxidation, inevitably caused the segregated Ge to form GeOx, leading to degradation of the interfacial quality of the gate stacks.We have used molecular beam epitaxy (MBE) to grow thin single-crystal Si of 0.79nm thickness (six MLs) epitaxially on epi-Si1-xGex(001) under ultra-high vacuum (UHV). Different from its counterpart of chemical vapor deposition (CVD), MBE enables epi-Si growth on Ge at growth temperatures below 300 °C. The measurements using reflection high-energy electron diffraction (RHEED), high-resolution synchrotron radiation X-ray diffraction (HR-XRD), and the scanning transmission electron microscopy with high-angle annular-dark-field (STEM-HAADF) have revealed high crystallinity of the epi-Si, the Si1-xGex layers and abrupt interfaces of the high-k/epi-Si/Si1-xGex layers. Moreover, our unique capability of epi growth/analysis enabled the study of the electronic surface structures of epi-Si/epi-Ge using in-situ high-resolution synchrotron radiation photoemission spectroscopy (SRPES) via a portable sample transfer station under UHV. We have used SRPES to demonstrate that the as-grown Si1−xGex(001)-2×1 surfaces with Ge content ranging from 0.1 to 0.9 are all terminated with buckled Ge–Ge dimers, and the surface electronic structure is similar to that of epi-Ge(001)-2×1. The direct deposition of epi-Si on as-grown SiGe removed the top buckled Ge-Ge dimers, which diffused into the epi-Si and some segregated to the top of the Si. As a result, the topmost layer beneath the epi-Si was 1 ML of Ge, and the interfaces of high-k/epi-Si/Si1−xGex are similar to those of the high-k/epi-Si/Ge. Again, the hetero-interfaces of our gate dielectrics are different from those grown using CVD.The well-controlled interfaces have enabled the achievement of low interfacial trap densities (Dit) of (3 - 6) × 1011 eV-1cm-2 in these high-k/epi-Si/Si1-xGex samples. The minimum Dit values remained at 3 × 1011 eV-1cm-2 regardless of the Ge content, demonstrating the effective passivation of the low-temperature deposited epi-Si. The limited Ge segregation during the low-temperature growth of epi-Si may attribute to the attainment of the low Dit values. We have benchmarked the minimum Dit (Dit, min) of our work with other state-of-the-art SiGe gate stacks. The Dit,min values from the other efforts increased with increasing Ge content, which may be caused by the GeOx formation that was difficult to control in the high-Ge-content (HGC) Si1-xGex.The effective charge sheet densities for the Si1-xGex gate stacks were extracted via examination of capacitance-voltage (C-V) hysteresis with decreasing stress voltage in the accumulation region of the MOS capacitors. We have attained very high acceleration factors of 8-12, indicating high reliability of the HfO2/epi-Si/Si1-xGex pMOS gate stacks.Furthermore, we have used a scavenging method, consisting of a cyclic process of an O2 exposure followed by a UHV annealing, to eliminate the segregated and diffused Ge in epi-Si before high-k deposition. Upon O2 exposure at room temperature, both the Si and Ge surface atoms are simultaneously oxidized to give rise to four Si charge states and Ge suboxides, respectively. The subsequent in-situ annealing at 500 °C under UHV moved the oxygen atom in the Ge suboxides to bond with the nearby Si atom. The annealing also caused the diffused Ge inside the epi-Si to segregate to the surface. The processes of O2 exposure followed by annealing were repeated three times resulting in an oxidized Si/Ge surface having only the four Si oxidized states without GeOx, but with a minimal amount of segregated Ge.

Improved Performance of Fully-Recessed High-Threshold-Voltage GaN MIS-HEMT With in Situ H₂/N₂ Plasma Pretreatment

In this letter, we demonstrate a high-threshold-voltage and high-current-density normally-off SiN/AlN/ GaN-on-Si MIS-HEMT with <i>in situ</i> low-damage H₂/N₂ plasma pretreatment. The <i>in situ</i> plasma pretreatment was performed in a plasma enhanced atomic layer deposition (PEALD) system prior to the PEALD-AlN deposition, which effectively suppress the interface trap densities between the AlN/GaN interface and increase the mobility of electrons to 198.80 cm<inline-formula> <tex-math notation="LaTeX">$^{{2}}/\text {V} \cdot \text {s}$ </tex-math></inline-formula>. Therefore, the devices demonstrate state-of-art characteristics with a competitive maximum drain current of 683.75 mA/mm at <inline-formula> <tex-math notation="LaTeX">${V} _{\textit {GS}} =15\text{V}$ </tex-math></inline-formula> and a high threshold of 6.28 V. The devices also show ON/OFF current ratio of <inline-formula> <tex-math notation="LaTeX">$10^{{8}}$ </tex-math></inline-formula> and off-state breakdown voltage of 1778 V.

Oxygen‐Scavenging Effects of Added Ti Layer in the TiN Gate of Metal‐Ferroelectric‐Insulator‐Semiconductor Capacitor with Al‐Doped HfO2 Ferroelectric Film

AbstractTi layer inserted in the TiN gate electrode effectively scavenges the oxygen in the low‐k interfacial SiO2 of the metal–ferroelectric–insulator–semiconductor (MFIS) capacitors with the ferroelectric Al‐doped HfO2 (HAO) thin film. The scavenging effect increases remanent polarization (Pr) and reduces coercive voltage (Vc) and capacitance equivalent thickness (CET) of the HAO films, particularly when the MFIS capacitor is annealed at 800 °C. Additionally, frequency dispersion of capacitance characteristics and interface trap density (Dit) calculations reveal that actively‐triggered oxygen‐scavenging effects also reduce defect or trap‐induced degradation. The Ti‐inserted MFIS structure exhibits fatigue‐free endurance and relatively low leakage current characteristics as compared to a structure without the Ti scavenging layer in high annealing temperature conditions required for crystallization of the HAO ferroelectric films.

Extracting interface trap density in &amp;beta;-Ga&amp;lt;sub&amp;gt;2&amp;lt;/sub&amp;gt;O&amp;lt;sub&amp;gt;3&amp;lt;/sub&amp;gt;-based heterointerface

<p indent="0mm">High performance devices need a high quality interface between metal/semiconductor, semiconductor/semiconductor or semiconductor/insulator. In this work, we report three different methods to obtain the interface trap density (<italic>D</italic>_it) in β-Ga₂O₃-based SBD, PN, and MOS capacitors. The characteristics of capacitance-voltage and conductance-voltage corresponding to frequency demonstrate a low <italic>D</italic>_it for Ni-SBD. Also, we introduce admittance spectroscopy (AS) to evaluate <italic>D</italic>_it of NiO/β-Ga₂O₃ PN diode. Moreover, the accurate high-low frequency capacitance method has been adopted for the MOS capacitor. The verified methods for extracting <italic>D</italic>_it offer a quantification of the quality of interface, which contribute to interface processing and device design.

Exciton dynamics and photoresponse behavior of the in situ annealed CsSnBr3 perovskite films synthesized by thermal evaporation

The CsSnBr3 photodetectors are fabricated by thermal evaporation and 75 °C in situ annealing, and the effect of in situ annealing on the morphology, structure, exciton dynamics and photoresponse of thermally evaporated CsSnBr3 films are investigated. Especially, temperature dependent steady-state photoluminescence (PL) and transient PL decaying have been analyzed in details for understanding the exciton dynamics. Meanwhile, effect of annealing on the activation energy for trap sites (E a), exciton binding energy (E b), activation energy for interfacial trapped carriers (ΔE), trap densities and carriers mobilities are studied and the annealed (A-CsSnBr3) reveals obviously lower E b and trap density together with notably higher carrier mobility than those of the unannealed (UA-CsSnBr3). Temperature dependence of the integrated PL intensity can be ascribed to the combining effect of the exciton dissociation, exciton quenching through trap sites and thermal activation of trapped carriers. The temperature dependent transient PL decaying analysis indicates that the PL decaying mechanism at low and high temperature is totally different from that in intermediate temperature range, in which combing effect of free exciton and localized state exciton decaying prevail. The beneficial effects of the in situ annealing on the photoresponse performance of the CsSnBr3 films can be demonstrated by the remarkable enhancement of the optimal responsivity (R) after in situ annealing which increases from less than 1 A W−1 to 1350 A W−1 as well as dramatically improved noise equivalent power, specific detectivity D* and Gain (G).

Positive Shifting of Vth with Enhanced DC Performance in AlGaN/GaN Schottky-Gate HEMT through Optimized UV/O3 Treated Gate Interface and Thermal Engineering

The surface condition under the gate is critically important to improve the device characteristics and thus reliability of the AlGaN/GaN high electron mobility transistor (HEMT). In this report, we demonstrated the reduction of leakage current (IG) with betterment of current collapse in Al0.25Ga0.75N/GaN Schottky gate (SG)-HEMT by improving metal/GaN interface using optimized ultraviolet-ozone (UV/O3) plasma treatment with post metal annealing modulation at 450 °C. The x-ray photoelectron spectroscopy (XPS) was used to verify the formation of GaOXNY layer at the metal/GaN interface. Owing to, the screening of the internal/external polarization charges by 10 min. UV/O3 surface plasma treatment and incremental increase of Schottky barrier height (Φ B) with post metal annealing modulation, resulted in the positive shifting of threshold voltage (VTH) in SG-HEMT. Due to the combined effects of the UV/O3 plasma treatment and metal annealing modulation, the magnitude of the interface trap density were effectively reduced to one order of magnitude, which further improved the current collapse significantly in SG-HEMT to 2.5% from 12.2%. The 10 min. UV/O3 treated SG-HEMT with PMA modulation exhibited decent performance with an IDMAX of 620 mA mm−1, a GMMAX of 135 mS mm−1, a threshold voltage (VTH) of −1.8 V, a higher ION/IOFF ratio of approximately a subthreshold swing (SS) of 83 mV dec−1, with a low gate leakage current of

Sensitivity of D&lt;sub&gt;it&lt;/sub&gt; Extraction at the SiO&lt;sub&gt;2&lt;/sub&gt;/SiC Interface Using Quasi-Static Capacitance-Voltage Measurements

In this work, we compare different quasi-static capacitance-voltage measurement systems by analyzing 4H-SiC n-type MOS capacitors and studying the influence of systematic errors when extracting the interface trap density (Dit). We show that the extracted Dit strongly depends on the calculation of the surface potential due to variations of the integration constant. In addition, the ramp-rate during the quasi-static measurement is identified as a sensitive measurement parameter whose noise level is amplified in the Dit extraction.

Chemical stoichiometry effect of hafnium oxide (HfOx) for passivation layer of PERC solar cells

Hafnium oxide (HfOx) is being investigated as a new candidate for the passivation layer of silicon solar cells due to its excellent electrical and optical properties, such as high dielectric constant, large band gap, refractive index, high transparency, and thermodynamic stability in contact with Si. In this paper, the HfOx is analyzed for novel material applied to the passivation layer to improve the performance of passivated emitter and rear contact (PERC) solar cells. For optimisation of the passivation layer of the PERC solar cell, chemical stoichiometry and passivation properties such as interface trap density, fixed charge and effective carrier lifetime are studied before and after the annealing process. After annealing in O2, interface trap density (Dit) decreased from 8.15 × 1010 eV−1cm−2 to 2.37 × 1010 eV−1cm−2 and the fixed charge (Qf) changed from positive to negative after annealing due to the reduction of oxygen vacancies. However, the passivation properties did not meet expectations due to blistering after annealing at 500 °C or higher and the highest effective carrier lifetime was 188.56 μs after annealing at 400 °C, which was improved from 49.48 μs before annealing. It was confirmed that improved passivation performance and solar cell efficiency could be achieved through the chemical stoichiometry effect by a simple annealing process.

Limiting Factors of Detectivity in Near-Infrared Colloidal Quantum Dot Photodetectors.

Lead sulfide colloidal quantum dots (PbS CQDs) have shown great potential in photodetectors owing to their promising optical properties, especially their strong and tunable absorption. However, the limitation of the specific detectivity (D*) in CQD near-infrared (NIR) photodetectors remains unknown due to the ambiguous noise analysis. Therefore, a clear understanding of the noise current is critically demanded. Here, we elucidate that the noise current is the predominant factor limiting D*, and the noise is highly dependent on the trap densities in halide-passivated PbS films and the carriers injected from the Schottky contact (EDT-passivated PbS films/metal). It is found that the thickness of CQDs is proportional to their interface trap density, while it is inversely proportional to their minimal bulk trap density. A balance point can be reached at a certain thickness (136 nm) to minimize the trap density, giving rise to the improvement of D*. Utilizing thicker PbS-EDT films broadens the width of the tunneling barrier and thereby reduces the carrier injection, contributing to a further enhancement of D*. The limiting factors of D* determined in this work not only explain the physical mechanism of the influence on detection sensitivity but also give guidance to the design of high-performance CQD photodetectors.

Characterization of interface properties of Al2O3/n-GaSb and Al2O3/InAs/n-GaSb metal-oxide-semiconductor structures

The interfacial InAs layers can improve the metal-oxide-semiconductor (MOS) interface properties of n-type GaSb (n-GaSb) MOS capacitors (MOSCAPs) with Al2O3 insulating layers deposited by an ex situ atomic-layer deposition (ALD) process. The n-GaSb MOSCAPs show the capacitance response in the accumulation region at RT, but they did not show the response with any low frequency at 100 K, indicating the quite high interface trap density (D it). On the contrary, the n-GaSb MOSCAPs with the interfacial InAs layers show sufficient accumulation responses at 100 K as well as RT, indicating the lower D it. The 1.5 nm thick InAs/n-GaSb MOSCAP with ALD-Al2O3 deposited at 150 °C exhibited relatively low D it of 2.6 × 1013 cm−2 eV−1, and the 2.5 nm thick InAs/n-GaSb MOSCAP with ALD-Al2O3 deposited at 300 °C exhibited low D it of 2.6 × 1012 cm−2 eV−1, while the 2.5 nm thick InAs layers can induce the delay of the response of electrons with the high frequency measurements at low temperature.

Gate Dielectric Treated by Self-Assembled Monolayers (SAMs) to Enhance the Performance of InSnZnO Thin-Film Transistors

Self-assembled monolayer (SAM) treatment of gate dielectrics is a standard process for manufacturing organic thin-film transistors (TFTs) to reduce interface trap density and surface energy. However, it is rarely used for oxide semiconductor-based TFTs because the SAMs may be damaged during the manufacturing process. To explore the feasibility of using a SAM-treated gate dielectric to improve the performance of oxide TFTs, we study the effects of different SAM treatments of the gate dielectric layer on the performance of InSnZnO (ITZO) TFTs, which can help guide the selection of SAMs. After treatment with methyltriethoxysilane (C1-SAM), the performance of the TFTs is significantly improved, showing a drastic improvement in the ON/ OFF ratio and carrier mobility, and a reduction of the interface trap density and <inline-formula> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> shift of the device under positive/negative bias stress (PBS/NBS). However, after treatment with n-octyltriethoxysilane (C8-SAM) and octadecyltriethoxysilane (C18-SAM), the performance of the TFTs deteriorate or even fail. Nevertheless, this work demonstrates an effective strategy for the construction of high-performance metal oxide TFTs, though it may require careful selection of the SAMs.

Studies on the electrical characteristics of a high-k dielectric/metal gate MOS capacitor by high-pressure annealing

In this work, a high-pressure annealing (HPA) technique at 6 atm over a wide range of temperatures (200 °C–450 °C) was used for post-metallization annealing on a high-k/metal gate MOS capacitor. To verify the ability of HPA to improve interface trap density and leakage issues another MOS capacitor with the same structure was annealed by microwave annealing (MWA) for comparison. The electrical performance of the capacitors under different annealing conditions were analyzed and the difference in characteristics such as flat-band voltage shift, oxide trapped charge, interface state density and leakage current were compared. HPA demonstrates a low trap density when compared with other annealing techniques, indicating potential removal of charge traps and a reduction in leakage current density. The results show that HPA is more effective at minimizing the oxide trapped charged at low temperature than MWA at 3000 W and the reduction in leakage current density after HPA at low temperatures corresponds to the reduction in charge traps. HPA at low temperature demonstrates great potential as a post-metallization annealing process for high-k/metal gate structures due to its ability to overcome undesired effects such as diffusion of Al into the dielectric layer.

Structural and electrical characteristics of ion-induced Si damage during atomic layer etching

Abstract Damage to the underlying Si substrate during the over-etching step of SiN atomic layer etching (ALE) was investigated. CH3F/Ar plasma was applied in the adsorption step, and Ar plasma in the desorption step. ALE increased interface trap density (D it), whereas Ar plasma did not affect D it. C, H, and F in the hydrofluorocarbon polymer, knocked-on by Ar, penetrated the Si substrate, which resulted in an increase in D it. Additionally, H in the polymer layer had a negligible impact on the damage caused by ALE. The H-penetration depth was shallow because the energy transferred from Ar to the H component in the polymer was low. Damage occurred only in the first cycle of ALE because a thick polymer layer, deposited after the second cycle, protected the substrate from additional damage. Thus, precise control of incident ion energy, adsorbed polymer thickness, and polymer composition are required to realize low-damage ALE.

Correlation between resistive switching characteristics and density of traps observed in Zr3N2 resistive switching memory devices with TiN barrier electrode

In this study, we present a correlation between the resistive switching (RS) characteristics and the traps of Zr3N2, which is based resistive random-access memory (RRAM) with a TiN barrier electrode, in order to identify the RS mechanism of the trap-based RRAM devices. First, gradual asymmetrical RS properties were discovered in the RS test, which included a current ratio of >2.51 × 102 and a large read margin of 480. As a result of analyzing the trap, the RS characteristics were deeply related to the nitride trap density (Nnt) in the Zr3N2 films as opposed to the interface trap density (Nit) at Zr3N2/p-Si layer. In addition, in the trap evaluation for four different resistance states, we observed that the Nnt was consistently increased with a decreasing resistance. These results indicate that the resistance state of the proposed TiN/Zr3N2/p-Si memory cell is determined by the Nnt, which means that controlling the Nnt is important in order to achieve a stable resistance state.

Experimental Investigation of Ultrathin Al₂O₃ Ex-Situ Interfacial Doping Strategy on Laminated HKMG Stacks via ALD

In this work, a p-type high-<inline-formula> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> metal gate (HKMG) with 3-nm interfacial Al₂O₃ doping HfO₂ laminated dielectric is presented to achieve the required gate electrode effective work function (EWF). Through the ex-situ interfacial doping strategy with various Al₂O₃ thickness, the electrical and interface characteristics of p-type HKMG MOSCAP are investigated. The results show that these parameters are strongly dependent on the thickness of the Al₂O₃. By increasing the Al₂O₃ thickness, the flat-band voltage (<inline-formula> <tex-math notation="LaTeX">${V}_{\text {FB}}$ </tex-math></inline-formula>) positive shift is elevated by 360 mV, and the trap/detrap electrons density (<inline-formula> <tex-math notation="LaTeX">${N}_{\text {ot}}$ </tex-math></inline-formula>) is significantly suppressed by an order of magnitude. In addition, the interface charge density (<inline-formula> <tex-math notation="LaTeX">${N}_{\text {SS}}$ </tex-math></inline-formula>) is significantly reduced, and interface trap density (<inline-formula> <tex-math notation="LaTeX">${D}_{\text {it}}$ </tex-math></inline-formula>), time-dependent dielectric breakdown (TDDB), and positive bias stress (PBS) is obviously improved. Finally, EWF modulation was increased from 4.976 to 5.206 eV (over the valence band edge of 5.17 eV). The results reveal that it is possible to tailor dielectric and electrical properties of high-<inline-formula> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> layers by adding a proper amount of interfacial Al₂O₃ doping into HfO₂, meeting the criteria required for gate electrode p-type EWF. These results and discussion provide an effective method for the integration of the HKMG stack in the MOSFETs and also useful for design of CMOS integration.

Theoretical study on the effect of electron transport layer parameters on the functionality of double-cation perovskite solar cells

Here, device modeling of FA0.83Cs0.17Pb (I0.6Br0.4)3 perovskite solar cell was performed. The band gap energy, electron affinity, and carrier concentration of the electron transport layer (ETL) have been investigated. Furthermore, ETL/perovskite interface defect density has been varied for this study. The study on electrical properties and the photovoltaic parameters of the perovskite solar cell showed that conduction band offset plays a vital role in cell performances. Furthermore, by increasing the electron affinity of ETL the cell performance decreased drastically, we attributed this result to an effective increase in the photogenerated carrier recombination in the ETL as well as ETL/front contact interface. Furthermore, simulation results disclosed a great dependence of PCE on the defect density at ETL/perovskite absorber interface layer. It was found that the role of interface trap density on decrement of Voc is dominant.

In-situ deposited HfO2 and Y2O3 on epi-Si/p-Ge—a comparative study of the interfacial properties and reliability

Single-crystal Si films six-monolayers in thickness were epitaxially grown on Ge(001) surface to minimize the formation of undesirable GeO x with subsequent deposition of HfO2 and Y2O3. The interfacial properties and reliability of the in-situ deposited high-κ oxides on epi-Si/p-Ge(001) were compared. We have achieved interface trap density (D it) values of (1–3) × 1011 eV−1cm−2 in the Y2O3/epi-Si/p-Ge(001), which are two times lower than those of the HfO2/epi-Si/p-Ge(001). The capacitance-equivalent-thicknesses under different annealing conditions were extracted to analyze the interdiffusion in the gate stacks under various thermal treatments. Y2O3/epi-Si/Ge exhibited higher thermal stability than HfO2/epi-Si/Ge. In both high-κ’s gate stacks, the effective charge sheet densities (ΔN eff) are lower than the targeted value of 3 × 1010 cm−2. Compared to the Y2O3 gate stacks, attainment of a high acceleration factor of 11 in the HfO2 gate stacks suggested an improved defect-carrier decoupling in the latter stacks.

Effect of hydrogen plasma treatment on the electrical properties for SiC-based power MOSFETs

This study investigates the effects of hydrogen plasma treatment on the leakage current and capacitance characteristics of metal–insulator–semiconductor (MIS) structures on SiC substrate. The H2 plasma treatment resulted in improved breakdown voltage and reduced defect density (Nd) in an atomic-layer-deposited 30 nm-thick Al2O3 (top)/15 nm-thick SiO2 bi-layer dielectric. The breakdown voltage in Al2O3/SiO2 bi-layer dielectric after H2 plasma treatment was improved by about 6.2% (initial 47 V). The value of Nd decreased by about one order in the Al2O3/SiO2 bi-layer dielectric from 2.3 × 1011/cm2 to 3.4 × 1010/cm2 after H2 plasma treatment. Further, the interface trap density (Dit) of Al2O3/SiO2 bi-layer dielectrics was 1.4 × 1012 cm−2·eV−1, and 50% of that of the SiO2 single dielectric film.

Impact of hydrogen plasma treatment on the electrical performances of ZnO thin-film transistors

In this study, we investigated the effects of hydrogen plasma (H) treatment on the structure, surface morphology, and optical and electronic properties of zinc oxide (ZnO) films, and on the performances of related ZnO thin-film transistors (TFTs). It was found that the performances and stabilities of the ZnO TFTs improved by carrying out the appropriate H plasma treatment. As a result, the ZnO:H (30 s) TFTs were found to exhibit a high field-effect mobility of 18.5 cm2/Vs, small threshold voltage (Vth) of 1.5 V, low sub-threshold swing of 0.32 V/decade, and high on/off current ratio (Ion/Ioff) of 107. These improvements could be attributed to the fact that the H treatment of ZnO was shown to result in the generation of shallow donors and in the defect passivation in ZnO films owing to the formation of HO and VO-H complex bounds. The increase in the carrier concentration and the passivation of the interface trap densities and oxygen vacancies in ZnO TFTs were revealed by X-ray photo-electron spectroscopy (XPS) analysis and density functional theory (DFT) calculations. These high-performance hydrogenated ZnO TFTs obtained as a result may find applications in oxide thin-film electronics.