Sensitivity of D<sub>it</sub> Extraction at the SiO<sub>2</sub>/SiC Interface Using Quasi-Static Capacitance-Voltage Measurements

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In this work, we compare different quasi-static capacitance-voltage measurement systems by analyzing 4H-SiC n-type MOS capacitors and studying the influence of systematic errors when extracting the interface trap density (Dit). We show that the extracted Dit strongly depends on the calculation of the surface potential due to variations of the integration constant. In addition, the ramp-rate during the quasi-static measurement is identified as a sensitive measurement parameter whose noise level is amplified in the Dit extraction.