Sigma-delta Research Articles

Time Encoding via Unlimited Sampling: Theory, Algorithms and Hardware Validation

An alternative to conventional uniform sampling is that of time encoding, which converts continuous-time signals into streams of trigger times. This gives rise to Event-Driven Sampling (EDS) models. The data-driven nature of EDS acquisition is advantageous in terms of power consumption and time resolution and is inspired by the information representation in biological nervous systems. If an analog signal is outside a predefined dynamic range, then EDS generates a low density of trigger times, which in turn leads to recovery distortion due to aliasing. In this paper, inspired by the Unlimited Sensing Framework (USF), we propose a new EDS architecture that incorporates a modulo nonlinearity prior to acquisition that we refer to as the modulo EDS or MEDS. In MEDS, the modulo nonlinearity folds high dynamic range inputs into low dynamic range amplitudes, thus avoiding recovery distortion. In particular, we consider the asynchronous sigma-delta modulator (ASDM), previously used for low power analog-to-digital conversion. This novel MEDS based acquisition is enabled by a recent generalization of the modulo nonlinearity called modulo-hysteresis. We design a mathematically guaranteed recovery algorithm for bandlimited inputs based on a sampling rate criterion and provide reconstruction error bounds. We go beyond numerical experiments and also provide a first hardware validation of our approach, thus bridging the gap between theory and practice, while corroborating the conceptual underpinnings of our work.

AI-Managed Cognitive Radio Digitizers

Embedding Artificial Intelligence (AI) in integrated circuits is one of the technology pillars of the so-called <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">digital transformation</i> . Nowadays, the vast majority of electronic devices benefits from digital signal processing to implement more and more functionalities, which can be further enhanced by the action of AI algorithms and artefacts. Moreover, as the analog/digital interfaces are moving closer and closer to the point where the information is either acquired or transmitted, the so-called AI-managed data converters are becoming key building blocks in an increasingly number of interconnected <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cyberphysical</i> systems–made up of both software and hardware components. Software Defined Radio (SDR) and Cognitive Radio (CR) systems intended for 5G/6G communications are good examples which can benefit from an early digitization managed by AI engines. <p xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">In this context, this paper presents an overview of circuits and systems techniques for AI-managed analog/digital interfaces with application in SDR/CR mobile telecom systems. Some design trends and challenges are discussed, going from new communications and computing paradigms for AIoT devices and networks, to digital-based/scaling-friendly analog circuit techniques for an efficient digitization. The state of the art on Analog-to-Digital Converters (ADCs) is surveyed, putting emphasis on highly-programmable Sigma-Delta Modulators (<inline-formula><tex-math notation="LaTeX">$\Sigma\Delta$</tex-math></inline-formula>Ms) as one of the best ADC candidates for SDR/CR transceivers. Some chip examples are shown to illustrate their potential application in AI-enhanced CR end-devices.

Binary Sequences for Online Electrochemical Impedance Spectroscopy of Battery Cells

Online diagnostic of lithium-ion battery (LIB) cells may have significant impact on chemical energy storage systems. Electrochemical impedance spectroscopy (EIS) is widely used for the characterization of LIBs and could be the most appropriate technique for online diagnostic, but its response time should be shortened. This work investigates the usage of multisine excitation to shorten the measurement time and simplify the hardware implementation for EIS of battery cells. Two types of multisine binary sequences are considered: sigma–delta modulated multisine sequences (SDMSs) and maximum length binary sequences (MLBSs). Their applicability to online and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in situ</i> EIS monitoring is evaluated by designing a measurement architecture also suitable to be implemented in a system-on-chip. The calibrated measurement system is compared with a benchtop reference instrument, reporting an RMSE deviation smaller than 5% in the frequency range of interest 1–200 Hz. The realized system is then used for online monitoring of the discharge process of a commercial 18650 LIB cell. The two proposed sequences are compared in terms of accuracy using a digital battery emulator circuit. Both the sequences demonstrated to be suitable for fast measurement and simple hardware integration, enabling online <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in situ</i> EIS monitoring at cell level.

An 8 bits, RF UHF-Band DAC based on interleaved bandpass delta sigma modulator assisted by background digital calibration

A multimode 8 to 4 bits delta sigma digital-to-analog converter (DAC) comprises a digital band-pass time interleaved delta sigma modulator (BP-TIDSM) with 2 interleaved channels in 5 frequency modes accompanied by a 4-bit analog DAC with a large SVR bandgap presented. As this interleaved modulator operates in narrow frequency channels around Fs/5, it leads to a low DCE design and there is no severe compulsion to calibrate which it leads to save power, area and hardware. Fully digital modulator design is modelled in MATLAB®/SIMULINK® and results in SNDR = 57 dB in 380, 420, 440, 460 MHz and 55 dB in 400 MHz with 1v supply voltage. In order to verify the results, this BP-TIDSM is synthesized by a behavioral VHDL code in ISE software and also Design compiler. Results are shown and compared in both MATLAB and ISE software. After noise shaping through the modulation and before multiplexing, a digital background calibration by a digital FIR filter applied to the modulator and all of them implemented by Cadence Virtuoso tool. A 4-bit analog DAC assigned to the multiplexer output to deliver a smooth analog signal. BP-TIDSM and calibration filters and also DAC circuits are implemented using Cadence in 180 nm technology. The proposed design used 52 mW of power with 1.6v output voltage swing and occupied an area of 0.121 mm2.

Modelling an oscillator phase noise whose spectral density contains both 1/f 2 and 1/f 3 regions

This paper introduces a new equation for modelling the phase noise spectrum of an oscillator. The new equation can model both of 1/f2 and 1/f3 regions in a phase noise spectrum. To verify the model and show its effectiveness, a mathematical analysis is performed on the effect of the oscillator phase noise on the performance of a continuous-time delta-sigma modulator. By comparing the results from the mathematical analysis with those from the Simulink simulation results, it is shown that using the proposed equation can properly predict the effect of oscillator phase noise on the modulator performance.

Improvement of sigma delta charge readout method for radiation detector application

Recently, a novel charge readout method has been developed based on 1-bit sigma delta modulation, which is able to directly achieve a Charge-to-Digital Conversion (QDC). This kind of design mainly comprises an amplifier and an FPGA instead of the conventional Front End Electronics (FEE) for radiation detectors. The amplifier is responsible for charge integration, and the FPGA is used for linear discharging. All of post-processing algorithms are implemented in the FPGA. Targeting this kind of readout method, some improvements are made to extend its application for new radiation detectors. In first improved version, a feedback resistor for baseline stabilization and a trigger threshold for removing noise signal are introduced. The feedback resistor leads to a slow exponential discharging when a charge signal is integrated on the feedback capacitor. To choose optimized parameters, an analysis of the exponential discharging effect on the linear discharging is made. In second version, an artful improvement is proposed to discard the exponential discharging. To evaluate the improved readout method, a 32-channel readout electronics prototype is developed. The performances and analysis of the circuit, such as channel linearity, dead time, are also presented. A SiPM based detector module is applied to verify this electronics prototype. The experimental results show that this new kind of charge readout is efficient and promising for other radiation detectors.

A 30.3 fA/√Hz Biosensing Current Front-End With 139 dB Cross-Scale Dynamic Range.

This paper presents an 8-channel array of low-noise (30.3 fA/√Hz) current sensing front-ends with on-chip microelectrode electrochemical sensors. The analog front-end (AFE) consists of a 1st-order continuous-time delta-sigma (CT ΔΣ) modulator that achieves 123 fA sensitivity over a 10 Hz bandwidth and 139 dB cross-scale dynamic range with a 2-bit programmable current reference. A digital predictor and tri-level pulse width modulated (PWM) current-steering DAC realize the equivalent performance of a multi-bit ΔΣ in an area- and power-efficient manner. The AFE consumes 50.3 µW and 0.11 mm2 per readout channel. The proposed platform was used to observe protein-ligand interactions in real-time using transient induced molecular electronic spectroscopy (TIMES), a label- and immobilization-free biosensing technique.

A Hybrid-Loop Structure and Interleaved Noise-Shaped Quantizer for a Robust 100-MHz BW and 69-dB DR DSM

A continuous-Time delta-sigma modulator (CT-DSM) excels at high-bandwidth (BW), high-dynamic-range analog-to-digital conversion. However, CT-DSMs suffer from PVT variation, high sensitivity to timing errors, and are restricted in sampling rate. This work proposes a hybrid-loop (HL) DSM architecture to mitigate the disadvantages of CT-DSM while providing similar performance. This work also introduces a bandpass time-interleaved noise-shaping (TINS) successive-approximation (SAR) architecture, which increases the sampling rate of TINS SAR. A prototype HL-DSM with bandpass TINS-SAR quantizer is built in 28-nm CMOS and occupies a die area of 0.09 mm². The measured peak SNDR is 67.5 dB for a 100-MHz BW. The total power consumption is 13.4 mW at a sampling rate of 1.6 GS/s. The resulting Schreier FoM of 166.2 dB is comparable to state-of-the-art CT-DSM converters.

A Microwave Quantum-Defined Millivolt Source

We demonstrate a tenfold increase in the amplitude of microwave-frequency waveforms generated by a quantum-defined superconducting voltage source, with an open-circuit signal of 17.56 mV rms at 1.005 GHz. The voltage source is an RF Josephson arbitrary waveform synthesizer (RF-JAWS) that utilizes a circuit that is cooled to 4 K and is composed of an array of 4500 Josephson junctions. These junctions are connected in series along the center conductor of a 50- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> superconducting coplanar waveguide transmission line. We introduce a new zero-forcing equalization technique for reducing distortion in drive current pulse patterns. This technique allows an increase in the amplitude of the quantum-based voltage waveforms while suppressing parasitic feedthrough signals to −75 dBc. Synthesizing a two-tone delta–sigma waveform, we monitor an audio-frequency 10-kHz tone of less than 100- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{V}$ </tex-math></inline-formula> rms amplitude while simultaneously measuring the 1.005-GHz tone of −28.12-dBm power in a 50- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> environment. The two-tone synthesis allows simultaneous verification of correct operation of the voltage source using time-efficient low-frequency measurement techniques as well as slower microwave measurements.

New 2 2 Sigma Delta Modulators for Different Applications

This work presents the design of a new 2-2 programmable sigma delta modulator architecture, for different applications, this transformation design of the ΣΔ modulator low-pass, band-pass and high-pass or vice versa with loopbacks addition, which improved the linearity of the converter and reduced the quantization noise. In this work, the MASH structure enables the implementation of stable and high-order modulator. This makes low voltage and low power applications ideal. The simulation result for sigma delta modulator for biomedical applications exhibit a signal to noise ratio is 95 dB @ 250Hz bandwidth and a 75dB @ 200KHz ,85dB @1MHz for pass band modulator. The SNR is about 70dB for 5MHz bandwidth and for high pass application. This tool will allow a development contribution and characterize a system optimization set from the start while remaining at a high level of design that is suitable for electronic systems and models VHDL-AMS, RF, Biomedical.

A high-precision interface for tunneling magnetoresistance sensors with 0.15 nT/√Hz resolution

The tunneling magnetoresistance (TMR) with high-resolution digital output is widely used in military and civil fields. In this work we proposed a low-noise read-out circuit and a four-order fully differential sigma-delta modulator for TMR sensors. In the read-out circuit, we used symmetrical cascade for good matching. We used correlated double sampling (CDS) technique to improve the conversion accuracy of the modulator. In switched capacitor circuits we used time-division multiplexing to suppress charge injection and clock feedthrough. The high-precision application specific integrated circuit (ASIC) chip was fabricated by a 0.35 [Formula: see text]m CMOS process from Shanghai Huahong foundry. The TMR sensor was placed in an environment of three-layer magnetic shielding for test. The active area of the ASIC is only about [Formula: see text]. At a sampling frequency of 20 kHz, the TMR magnetometer consumes 77 mW from a single 5 V supply; the sigma-delta modulator for TMR can achieve an average noise floor of −141 dBV. The magnetometer works at a full scale (FS) of [Formula: see text], it can achieve a nonlinearity of 0.2% FS and a resolution of 0.15 nT/Hz[Formula: see text] over a signal bandwidth.

Channelized active noise elimination (CANE) for suppressing quantization noise in bitstream modulated transmitter (BMT)

Bitstream modulated transmitters may offer improved power efficiency and linearity simultaneously in RF power amplifiers. Several modulation techniques including envelop delta-sigma modulation and envelope pulse width modulation have been applied. The out-of-band quantization noise associated with these modulations may be rejected by a high-quality factor output filter, yet the in-band quantization noise needs to be further suppressed to meet the requirement of the emission mask. The proposed channelized active noise elimination technique can offer additional quantization noise suppression through software control without involving a passive filter. The essential concept is based on combining the outputs of multiple channels of Pas that have digitally controlled delays to form a FIR filter in analogue domain. A two-channel and a four-channel GaN power amplifiers are built to demonstrate this noise suppression concept and power combiners based on T-junction with quarter wavelength transmission line are proposed to retain the high power efficiency of the transmitters.

Multifrequency Modulation to Achieve an Individual and Continuous Power Distribution for Simultaneous MR-WPT System With an Inverter

To achieve an individual and continuous power distribution for multireceiver wireless power transfer (WPT) systems, a novel multifrequency modulation method has been proposed. In the proposed method, a look-up table and delta-sigma modulation scheme are introduced to generate a mixed-frequency driving voltage pulse by synthesizing it from the given voltage pulses. The components of synthesized driving voltage pulse have continuously and individually varying amplitudes of multiple specific frequencies. With the proposed modulation method, only a standard full-bridge inverter is employed in the transmitting side to achieve power distribution among receivers, leading to a simple configuration of the transmitting source. Moreover, the proposed method has a small calculation burden and can be easily extended to the system with more receivers. When compared with the existing multifrequency modulation method, a lower switching frequency is obtained in the proposed method. Finally, the effectiveness of the proposed modulation method is verified theoretically and experimentally.

Application of a sigma-delta modulator for adiabatic charging of an output stage capacitor

ABSTRACT In energy harnessing applications there are instances where energy should be transferred from a low-power, low-leakage backup battery to a temporary power delivery output capacitor. The high power delivery feature of the storage capacitor usually comes at the price of higher leakage current and thus it cannot replace the long-term energy storage backup battery. This paper presents a CMOS capacitor charger circuit which connects a long term low power battery to a short-burst high power delivery capacitor. The proposed circuit uses a switching output stage with an external inductor to reduce the dissipation during the capacitor charge-up cycle. A sigma-delta modulation approach is used to control the power switches. Under low power transfer scenarios which perform transfer in a longer duration, the proposed approach shows better performance compared with previously presented techniques. It is shown that under different transfer durations the control section only consumes 970nWs. The efficiency of the proposed circuit is more than 90% for average input powers in the 0.7 mW to 2 mW range.

A novel system-level modeling and design approach for high performance single-loop sigma-delta (∑Δ) modulators

PurposeThis paper attempted a novel approach for system-level modeling and simulation of sigma-delta modulator for low-frequency CMOS integrated analog to digital interfaces. Comparative analysis of various architectures topologies, circuit implementation techniques are described with analytical procedure for effective selection of topologies for targeted specifications.Design/methodology/approachVirtual instruments are presented in labview environment to analyze the correlation of circuit-level non-ideal effects with key design parameters over sampling ratio, coarse quantizer bits and loop filter order. A fourth-order single-loop sigma-delta modulator is designed and verified in MATLAB simulink environment with careful selection of integrator weights to meet stable desired performance.FindingsThe proposed designed achieved SNDR of 122 dB and 20 bit resolution satisfying high-resolution requirements of low-frequency biomedical signal processing applications. Even though the simulation performed at behavioral level, the results obtained are considered as accurate, by including all non-ideal and non-linear circuit errors in simulation process.Originality/valueVirtual instruments using labview environment used to analyze the correlation of circuit-level non-ideal effects with key design parameters over sampling ratio, coarse quantizer bits and loop filter order for accurate design.

Power Electronics Programmable Voltage Source with Reduced Ripple Component of Output Signal Based on Continuous-Time Sigma-Delta Modulator

In this work, an idea of a wideband, precision, power electronics programmable voltage source (PVS) is presented. One of the basic elements of the converter, the control section, contains a continuous-time sigma-delta modulator (SDM) with a pair of interconnected complementary comparators, which represents a new approach. In this case, the SDM uses comparators with a dynamic hysteresis loop (DHC) that includes an AC circuit rather than an R-R network. Dynamic hysteresis is a very effective way of eliminating parasitic oscillation during the signal transition at the input of the comparator; it also affects the frequency characteristics and, especially, the phase properties of the comparator, and this phenomenon is exploited in the proposed converter. The main disadvantage of all pulse-modulated converters is the presence of a ripple component in the output voltage (current), which reduces the quality of the output signal and may cause high-frequency disturbances. A basic feature of PVS is a lower RMS value for the pulse modulation component in the output voltage of the converter, compared to the typical value. Another important feature of the proposed converter is the ability of precise mapping of the output voltage to the reference (input) signal. The structure of the control circuit is relatively simple—no complex, digital components are used. Due to the high frequency of the SDM output bit-stream, the simulation model of the power stage of PVS is based on the power modules with gallium-nitride field effect transistors (GaN FETs). The work discusses the rules of PVS operations and the results from PVS simulation model studies as well as highlights the possible application fields for systems with a PVS.

Current Sensing Front-Ends: A Review and Design Guidance

Sensors link the physical and electronic worlds, finding uses in environmental, automotive, industrial, communication, and medical applications, among many more. Here, current-output sensors and current-sensing front-ends are reviewed, aiming to provide readers comprehensive design guidance from both sensor and circuit perspectives. Starting from the transduction method, capacitive, resistive, diode/FET-based, and MEMS sensors are individually reviewed with a focus on applications, circuit models, and nonidealities that must be considered for the front-end design. This is followed by a discussion of current-sensing front-ends, including transimpedance amplifiers (TIAs), current conveyors (CC), current-to-frequency ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}$ </tex-math></inline-formula> -to- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${F}$ </tex-math></inline-formula> ) converters, and current-mode delta-sigma (I- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> ) modulators. Each front-end is analyzed in terms of gain, bandwidth, stability, noise, and general design considerations are presented. State-of-the-art works for each front-end are then reviewed, and tradeoffs between different architectures are discussed.

A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator.

Sampling-based PLLs have become a new research trend due to the possibility of removing the frequency divider (FDIV) from the feedback path, where the FDIV increases the contribution of in-band noise by the factor of dividing ratio square (N2). Between two possible sampling methods, sub-sampling and reference-sampling, the latter provides a relatively wide locking range, as the slower input reference signal is sampled with the faster VCO output signal. However, removal of FDIV makes the PLL not feasible to implement fractional-N operation based on varying divider ratios through random sequence generators, such as a Delta-Sigma-Modulator (DSM). To address the above design challenges, we propose a reference-sampling-based calibration-free fractional-N PLL (RSFPLL) with a phase-interpolator-linked sampling clock generator (PSCG). The proposed RSFPLL achieves fractional-N operations through phase-interpolator (PI)-based multi-phase generation instead of a typical frequency divider or digital-to-time converter (DTC). In addition, to alleviate the power burden arising from VCO-rated sampling, a flexible mask window generation method has been used that only passes a few sampling clocks near the point of interest. The prototype PLL system is designed with a 65 nm CMOS process with a chip size of 0.42 mm2. It achieves 322 fs rms jitter, −240.7 dB figure-of-merit (FoM), and −44.06 dBc fractional spurs with 8.17 mW power consumption.

A 5 MHz-BW 71.7-dB SNDR two-step hybrid-domain ADC in 65-nm CMOS

This paper proposes a second-order sigma-delta two-step hybrid-domain ADC comprises of a SAR ADC, a voltage-to-time converter (VTC), and a second-order sigma-delta TDC with all the arithmetic circuits based on the time-registers implemented in time-domain, and the TDC achieves pole-optimization using a method similar to the voltage-domain noise shaping ADC. The SAR ADC samples the input signal and performs the coarse quantization in voltage-domain. Then the residual voltage is transferred into the time signal by the VTC and the TDC completes the fine quantization in time-domain. The prototype ADC is implemented in TSMC 65 nm 1P9M 1.2 V standard CMOS process. The simulated SFDR and SNDR are 75.7 and 71.7 dB with an oversampling ratio of 10 while consuming 4.8 mW at 100 MS/s.

Short Word-Length Entering Compressive Sensing Domain: Improved Energy Efficiency in Wireless Sensor Networks

This work combines compressive sensing and short word-length techniques to achieve localization and target tracking in wireless sensor networks with energy-efficient communication between the network anchors and the fusion center. Gradient descent localization is performed using time-of-arrival (TOA) data which are indicative of the distance between anchors and the target thereby achieving range-based localization. The short word-length techniques considered are delta modulation and sigma-delta modulation. The energy efficiency is due to the reduction of the data volume transmitted from anchors to the fusion center by employing any of the two delta modulation variants with compressive sensing techniques. Delta modulation allows the transmission of one bit per TOA sample. The communication energy efficiency is increased by RⱮ, R ≥ 1, where R is the sample reduction ratio of compressive sensing, and Ɱ is the number of bits originally present in a TOA-sample word. It is found that the localization system involving sigma-delta modulation has a superior performance to that using delta-modulation or pure compressive sampling alone, in terms of both energy efficiency and localization error in the presence of TOA measurement noise and transmission noise, owing to the noise shaping property of sigma-delta modulation.