Sigma-delta Research Articles

A 10-MHz 85.1-dB SFDR 1.1-mW continuous-time Delta–sigma modulator employing calibration-free SC DAC and passive front-end low-pass filter

This article demonstrates the circuit technique of a highly power-efficient continuous-time (CT) Delta–sigma modulator (DSM) based on a switched-capacitor (SC) feedback digital-to-analog converter (DAC) and a passive front-end low-pass filter (LPF). The technique addresses the clock sensitivity issue of conventional DACs while maintaining the alias rejection. It is validated by a fourth-order CT DSM prototype fabricated in 65-nm CMOS technology. The input stage of the DSM is an active-RC integrator merged with a passive front-end LPF. A resonator follows and realizes the cascade of resonators with feedforward (CRFF) structure. The accurate feedback loop employs a highly linear and calibration-free 5-level SC DAC. Based on the linear periodically time-varying (LPTV) system model, an exact analysis is given to explain the effects of the passive LPF and SC DAC combo on the signal transfer function (STF), and hence, on the alias rejection. The prototype DSM achieves a 70.2-dB signal to noise and distortion ratio (SNDR) and an 85.1-dB spurious-free dynamic range (SFDR) in a 10-MHz bandwidth, while dissipating 1.1 mW with a 1-V supply. The modulator achieves a 65.4-dB alias rejection and confirms the closed-form analytical results.

Demonstration of 4096QAM THz MIMO wireless delivery employing one-bit delta-sigma modulation.

We experimentally demonstrate 2-Gbaud 4096-ary quadrature amplitude modulation (4096QAM) signal transmission over 2-m wireless distance at 370 GHz in a photonics-aided terahertz (THz)-wave communication system. By using one-bit quantized delta-sigma modulation (DSM) and photonics-aided technology, we successfully achieve the transmission of high-order QAM signals over THz multiple-input multiple-output (MIMO) links. After 2 m of free space transmission, its bit error rate (BER) is below the 20% soft-decision forward error correction (20% SD-FEC) threshold of 2.4 × 10-2. To the best of our knowledge, this is the first time to apply DSM technology in a THz MIMO link transmission.

Macro Model for Discrete-Time Sigma‒Delta Modulators

This work presents a macro model for discrete-time sigma‒delta modulators, which can significantly reduce the simulation time compared to transistor level circuits. The proposed macro model is realized by effectively combining active and passive ideal circuit components with Verilog-A modules. As such, since the macro model is a true representation of the actual transistor level circuit, a moderately good accuracy can be obtained. In addition, the proposed macro model includes the major amplifier, comparator, and switch‒capacitor non-idealities of the sigma‒delta modulator such as amplifier DC gain, GBW, slewrate, comparator bandwidth, hysteresis, parasitic capacitance, and switch-on resistance. The results show the simulation time of the proposed macro model sigma‒delta modulator is only 6.43% of the transistor level circuit with comparable accuracy. As a result, the proposed macro model can facilitate the circuit design and leverage non-ideality analysis of discrete-time sigma‒delta modulators. As a practical design example, a second order discrete-time sigma‒delta modulator with a five-level quantizer is realized using the propose macro model for GSM and WCDMA applications.

Real-Time Experimental Demonstration of Hybrid FSO/Wireless Transmission Based on Coherent Detection and Delta-Sigma Modulation

For the fronthaul link in the fifth-generation (5G) wireless networks, optical fiber is one of the most widely used medium, owing to its large bandwidth and low transmission loss. However, in some scenarios, especially the dense urban areas, the installation of fiber optic cables is costly and difficult to establish. Alternatively, the free space optical (FSO) link can be installed easily and spans complex terrain. In this context, we propose and experimentally demonstrate a hybrid FSO/Wireless transmission system based on bandpass delta-sigma modulator and real-time coherent transponder. Advantage of the proposed technique is twofold. Firstly, coherent detection is applied to improve the system sensitivity compared to conventional direct detection. Secondly, delta-sigma modulation (DSM) is utilized to greatly simplify the wireless transmitters and to enhance the bandwidth flexibility. Over a 50-m FSO and 1-m wireless link, a 64-QAM wireless signal at 1 GHz with 500 MHz bandwidth is successfully transmitted. With 16 wavelength division multiplexing channels, the total throughput of the system is up to 24 Gb/s. Meanwhile, the error vector magnitude (EVM) of all channels is around 2.68% and 6.51%, which are demonstrated after FSO and FSO/Wireless transmission, respectively. The results meet the requirement of the third-generation partnership project release 15 with EVM value of 8% for 64-QAM. Moreover, sensitivity of the real-time coherent receiver is lower than −48 dBm under the 7% forward error correction limit with bit error rate of 3.8e-3.

Self-Calibrated Digital Two-Point Modulator for BLE RF Transmitter

In this brief, a self-calibrated two-point delta-sigma modulation technique for a CMOS RF transmitter is proposed for use for a voltage-controlled oscillator (VCO) and a delta–sigma modulator in a frequency synthesizer. By using the counter to calibrate the frequency deviation of two-point modulation to the desired value, the gain mismatch between two paths can be completely calibrated by modifying the gain of the VCO path. The frequency modulation therefore guarantees a robust performance against PVT variations without using any additional circuit. This technique is applied to Bluetooth Low Energy (BLE) applications. The proposed Two-Point Modulation achieves error vector magnitude (EVM) of −29.3 dB at 1 Mbps and is implemented in 55 nm CMOS process technology. The area of the chip is 0.28 mm2 and its power consumption is 2.9 mW.

A New Space Vector Pulse Density Modulation Scheme for Two-Level Five Phase Induction Motor Drive

Variable speed drives incorporating multiphase motors have started gaining attention in recent years due to their benefits over three-phase counter parts. In this article, we propose a digital control scheme based on space vector pulse density modulation for two-level five phase induction motor drive. The scheme combines principles of digital signal processing techniques, such as sigma delta modulation and vector quantization, along with space vector modulation to form computationally efficient motor drives. In this article, vector space is divided into ten nonoverlapping regions, with each region partitioned into three voronoi regions. The reference vector is vector quantized to the nearest switching vector. Absence of dwell time calculations, less memory requirements, and reduced computational complexity of the scheme along with reduced acoustic noise and electromagnetic interference in the drive are the core advantages of the scheme. The work has been experimentally implemented with 2 HP five-phase induction motor drive and the results are compared with space vector pulsewidth modulation scheme for validation purpose.

An 18.1 mW 50 MHz-BW 76.4 dB-SNDR CTSDM With PVT-Robust VCO Quantizer and Latency-Free Background-Calibrated DAC

This paper presents a continuous-time sigma-delta modulator (CTSDM) with a voltage-controlled-oscillator-based (VCO-based) integrating quantizer. A background replica-based calibration technique is proposed to alleviate the impact of the process, voltage supply, and temperature (PVT) variations on the tuning characteristic and current consumption of the VCO-based quantizer. Matching between the replica VCO and the main VCO in the proposed calibration is not needed. A latency-free background calibration technique is also proposed to eliminate the distortions caused by the DAC mismatch. The prototype VCO-based CTSDM is fabricated in a 40 nm CMOS and achieves SNDR/SFDR/DR of 76.4 dB/91.7 dBc/79.6 dB, respectively, within a 50 MHz bandwidth (BW) at 1.6 GHz sampling frequency. The measured SNDR varies within ±1 dB over a temperature range of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0\sim 80~^{\circ }\text{C}$ </tex-math></inline-formula> and a voltage supply variation of ±10%, across different tested samples. The power consumption is 18.1 mW, achieving a Schreier Figure of Merit (FoMS) of 170.8 dB.

A 28-nm 6-GHz 2-bit Continuous-Time ΔΣ ADC With −101-dBc THD and 120-MHz Bandwidth Using Blind Digital DAC Error Correction

In this article, a 6-GHz, 2-bit, fourth-order continuous-time delta–sigma (CT <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> ) analog-to-digital converter (ADC) fabricated in 28-nm CMOS is presented. It achieves −101- and −105-dBc total harmonic distortion (THD)/third-order inter-modulation (IM3) typically and 72.3-dB signal to noise and distortion ratio (SNDR) in 120-MHz bandwidth (BW). The ADC comprises four cascaded integrators with inverter-based amplifiers, an offset compensated 2-bit quantizer, and calibrated 2-bit feedback (FB) digital-to-analog converter (DAC). The DAC and quantizer employ blind digital calibration techniques enabling the wideband linearity performance. The ADC does not require any external test signal during calibration. The power dissipation of the modulator core, including demultiplexer, is 108.8 mW.

4th Order LC-Based Sigma Delta Modulators.

Due to the characteristic of narrow band conversion around a central radio frequency, the Sigma Delta Modulator (ΣΔM) based on LC resonators is a suitable option for use in Software-Defined Radio (SDR). However, some aspects of the topologies described in the state-of-the-art, such as noise and nonlinear sources, affect the performance of ΣΔM. This paper presents the design methodology of three high-order LC-Based single-block Sigma Delta Modulators. The method is based on the equivalence between continuous time and discrete time loop gain using a Finite Impulse Response Digital-to-Analog Converter (FIRDAC) through a numerical approach to defining the coefficients. The continuous bandpass LC ΣΔM simulations are performed at a center frequency of 432 MHz and a sampling frequency of 1.72 GHz. To the proposed modulators a maximum Signal-to-Noise Ratio (SNR) of 51.39 dB, 48.48 dB, and 46.50 dB in a 4 MHz bandwidth was achieved to respectively 4th Order Gm-LC ΣΔM, 4th Order Magnetically Coupled ΣΔM and 4th Order Capacitively Coupled ΣΔM.

A Single-Bit Incremental Second-Order Delta-Sigma Modulator with Coarse-Fine Input Buffer

This paper presents an incremental second-order delta-sigma modulator with a coarse-fine input buffer in 180-nm CMOS. The modulator’s architecture was implemented as a second-order cascade of integrators with a feedback structure. The switched-capacitor integrator was operated in discrete time, with high-gain amplifiers required to achieve improved performance during the integration phase. The amplifier comprised rail-to-rail input and gain-boosted cascode intermediate stages, thus achieving a high gain and wide input voltage range. The circuit adopts a coarse-fine buffer for higher performance. The coarse buffer is operated first to enable fast settling through a high slew rate, followed by the fine buffer to satisfy the low-noise and high-accuracy characteristics. The fine buffer has a smaller current consumption with higher power efficiency. The experiment results show that the proposed input buffer achieved a 13.14 effective number of bits and an 80.87 dB signal-to-noise and distortion ratio. The modulator operates a single bit and sampling clock at 125 kHz. The proposed delta-sigma modulator was operated at 1.8 V. The proposed circuit was designed using a standard 0.18-μm CMOS process with an active area of 1.06 mm2. The total current consumption with the coarse-fine buffer was 1.374 mA.

ASHP-Association of Black Health-System Pharmacists Joint Leadership Award.

Angela Massey Hill, PharmD, CPh, RPh, is the 2022 recipient of the ASHP–Association of Black Health-System Pharmacists (ABHP) Joint Leadership Award. The award was established in 2009 to recognize people whose exceptional leadership has helped reduce racial and ethnic disparities in healthcare. Hill is associate dean and professor of pharmacy at the University of South Florida (USF) Health Taneja College of Pharmacy in Tampa. Her clinical work focuses primarily on neuropsychiatric conditions and gerontology. She has worked throughout her career to improve the care of people with dementia and to educate patients, clinicians, and caregivers about dementia and other memory disorders. She practices as a clinician at Reliance Medical Centers, where she provides medication therapy management and works with the organization’s Brain Health Awareness Program. She is also a consultant for the USF Neuroscience Byrd Alzheimer’s Institute. Hill was the 2004 recipient of a research endowment from Delta Sigma Theta Inc. for the investigation of biomarkers associated with Alzheimer’s disease in African Americans. The award launched and continues to drive her research agenda.

A real-time embedded system to detect QRS-complex and arrhythmia classification using LSTM through hybridized features

The electrocardiogram (ECG) is an extremely valuable medical examination for monitoring cardiac disorders. The QRS waves on the ECG signal are essential in diagnosing these disorders. While numerous algorithms for detecting R-peaks/QRS complexes are developed, most are focused on complex computations that need off-line execution on a PC. However, advancements in telemedicine and wearable devices require an algorithm that runs effectively on an embedded system. This paper aims to design and develop an embedded system to detect the QRS complex and arrhythmia classification based on the patient-specific ECG data. The proposed model is based on the Discrete Wavelet Transform (DWT), Delta Sigma Modulation (DSM) with local maximum/minimum point algorithm to detect R peak/QRS complex. It extracts several R peaks/QRS complex features, such as the waves peak, onset, offset, and duration between consecutive R peaks (RR interval), and uses these to improve classification accuracy. We proposed Long Short Term Memory (LSTM) neural network for arrhythmia classification. First, the ECG signal is extracted through the embedded system and used for further processes. Second, the QRS complex/R peak is detected using modulated bitstreams, threshold level through DSM and DWT, respectively. Thirdly, the extracted features are hybridized and input into an LSTM for arrhythmia classification. The MIT-BIH database was used to evaluate the algorithm’s performance, and the accuracy, positive predictivity, sensitivity, and F1 score were evaluated as performance metrics. The algorithm achieved 99.64 %, 99.15 %, 99.87 %, and 98.18 % for all four metrics, respectively. The algorithm was then executed on an embedded system, and its run time and power consumption were examined. The DSM algorithm detects QRS waves in 17.2 ms, while the DWT method detects R peak in 14.02 ms. The proposed LSTM algorithm takes 58 ms for classification. The DSM chip (MCP3008 ADC) consumes 680 nW of power at a sampling rate of 500 Hz. Additionally, the algorithm’s performance was compared to those of other widely used algorithms. The suggested approach holds considerable promise for long-term monitoring in wearable systems.

A very low-power discrete-time delta-sigma modulator for wireless body area network

This paper proposes a very low-power discrete-time delta-sigma modulator (DTDSM) for the wireless body area network (WBAN) which deals with biomedical signals. The first stage integrator is optimized using correlated double sampling technique and is implemented using a high-gain designed telescopic operational transconductance amplifier (OTA) in order to maintain the proposed second-order DTDSM high resolution. In order to keep both stage integrators active and prevent ENOB loss, a very low power two-stage charge-steering amplifier is employed in the second stage integrator which leads to a power efficient design. Due to not high but enough voltage-gain of this type of amplifier, the proposed charge-steering-based integrator leads to a negligible loss of ENOB in comparison to passive integrators with no voltage gain which are commonly used in the second stage to reduce the total power. In fact, due to the combination of a high-gain OTA in first stage integrator and a low-power charge-steering amplifier in second stage, compromise between high resolution and low power consumption will be depicted.The proposed DTDSM is designed for a signal bandwidth of 50 kHz with an oversampling ratio of 128 for implantable biomedical devices in the MICS band. Simulations are done using TSMC 180 nm technology at a 1.8 V power supply. Simulation results illustrate that the designed modulator achieves an SNR of 56 dB which is equal to 9 bits of ENOB that is in the desired range for biomedical signals. The power consumption of this modulator is only 142 μW at a 12.5 MHz sampling frequency.

A Novel Structure Optimizer Based on Heuristic Search for Delta-Sigma Modulator in Mobile Fronthaul

In this letter, a novel delta-sigma modulator structure design method based on the genetic algorithm is proposed. Compared to the widely adopted R.Schreier’s method, the proposed approach can significantly reduce the in-band quantization noise. Performance comparisons are carried out on 4th-order baseband delta-sigma modulators (DSMs) and 6th-order bandpass DSMs with center frequency at 2GHz. OSR of these delta-sigma modulators are set at 8. Numerical simulations, as well as experimental demonstrations, are conducted to show a 10-Gbaud intensity modulation direct detection transmission with the 64-QAM signal. Experimental results show that compared to R. Schreier’s method, the proposed GA method can improve the SNR by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 5$ </tex-math></inline-formula> dB and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 3$ </tex-math></inline-formula> dB for baseband DSM and bandpass DSM, respectively.

Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier

This article presents a delta–sigma modulator (DSM) using a cascoded floating-inverter-based dynamic amplifier. The proposed cascoded dynamic amplifier achieves more than 50-dB dc gain while maintaining an HD3 of better than –110 dBc for signal swings less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$300~\mathrm {mV_{ppd}}$ </tex-math></inline-formula> . Compared to the previously reported two-stage floating inverter amplifier (FIA), the cascoded FIA has a lower and a process invariant input-referred noise, making it an ideal choice for high-resolution ADCs. We also show that, when such a single-stage dynamic amplifier, which has a time-varying transconductance, is used in closed-loop switched-capacitor circuits, the settling bandwidth depends on the average transconductance <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m,\rm avg}$ </tex-math></inline-formula> during the settling interval. A detailed analysis reveals that, when the floating inverter structure operates in weak inversion for most of the time (which is the power-efficient way to bias the amplifier), this average transconductance depends strongly on the reservoir capacitance value and only weakly on the transistor dimensions. Besides, it is less sensitive to temperature variations, unlike the transconductance of a conventional OTA biased in weak inversion. We also quantitatively derive and show that the cascoded FIA is more power-efficient than a conventional static-current biased operational transconductance amplifier. Using the cascoded FIA, a discrete-time DSM has been designed and fabricated in a 180-nm CMOS process. The modulator runs at 3.072 MHz while consuming 189 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> from a 1.8-V supply. In a bandwidth of 24 kHz, the measured SNR/SNDR/SFDR is 96.4/96.2/114 dB, respectively.

A 2.16-μW Low-Power Continuous-Time Delta–Sigma Modulator With Improved-Linearity Gₘ for Wearable ECG Application

This brief presents a 2.16 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> low-power third-order single-bit continuous-time delta-sigma modulator (CTDSM) for electrocardiogram (ECG) signal acquisition application. The proposed CTDSM uses an active-RC (A-RC) integrator as a first integrator and an improved linearized <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m}$ </tex-math></inline-formula> -C integrator for the second and third integrators, respectively. The mixed-integrator structure helps to mitigate the trade-offs between power consumption and resolution. Moreover, a source-degenerated auxiliary differential pair circuit is used for the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m}$ </tex-math></inline-formula> -C integrators to improve their linearity. By using A-RC and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m}$ </tex-math></inline-formula> -C integrators together along with an improved-linearized <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m}$ </tex-math></inline-formula> block, the total power consumption was measured as 2.16 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> with a peak signal-to-noise ratio of 80.1 dB, signal-to-noise, and distortion ratio of 78.4 dB, and a dynamic range of 81.4 dB with a bandwidth of 250 Hz. Furthermore, a real-time ECG signal was successfully captured in an ECG acquisition system that consisted a heart-rate sensor and a signal acquisition circuit, including the proposed CTDSM.

Design of High-Resolution Continuous-Time Delta–Sigma Data Converters With Dual Return-to-Open DACs

We present design techniques for single-bit continuous-time delta–sigma modulators that attain high resolution (>16 bits) over a bandwidth (BW) that is more than ten times the audio range. We introduce the zapped, virtual-ground-switched dual return-to-open DAC which is immune to ISI and other transition-dependent errors. FIR feedback facilitates chopping, improves clock-jitter sensitivity and the loop filter’s linearity. We show that the compensation FIR DAC, which is typically bulky, can be implemented in an extremely power- and area-efficient manner in a single-bit modulator using a capacitive DAC and passive summation. Thanks to these techniques, the fabricated prototype achieves 103.2-/104.3-dB signal to noise and distortion ratio (SNDR)/signal to noise ratio (SNR) in a 250-kHz bandwidth while operating at 48 MS/s. Consuming 17.7 mW from a 1.8-V supply, the modulator occupies 1.1 mm 2 in a 180-nm CMOS process. The Schreier (SNDR) figure of merit (FoM) is 174.7 dB.

A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta–Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS

This article shows the design of a wideband 3-0 sturdy-multi-stage noise-shaping (SMASH) continuous-time (CT) incremental delta–sigma (I- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {\Delta \Sigma }$ </tex-math></inline-formula> ) analog-to-digital converter (ADC). The two stages’ quantizers (QTZs) are implemented by a single re-configurable multibit (MB) asynchronous (A)SAR ADC. The digital-to-analog converter (DAC) nonlinearities are suppressed by reconfiguring the asynchronous successive-approximation register (ASAR) ADC from 2 to 5 b, and correspondingly, the DACs dynamically switch from 1.5- to 4-b tri-level outputs within each Nyquist conversion cycle. This results in a DAC-calibration-free MB operation. A two-tap FIR filter is implemented in the feedback DACs to reduce jitter requirements in the initial 1.5-b cycles. Through the design representation, a detailed fundamental comparison between an X-0 SMASH architecture and an X-order single-loop modulator is discussed. This discussion highlights the introduction of an efficient tri-level combination between the MSB and the LSBs of the ASAR QTZ. The resulting SMASH CT I- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {\Delta \Sigma }$ </tex-math></inline-formula> modulator was fabricated in 28-nm CMOS technology with an active area of 0.125 mm2. It achieves 97-dB spurious-free dynamic range (SFDR) without calibration, 89-dB dynamic range (DR), and 81.2-dB SNDR in a 1-MHz bandwidth (BW). It consumes 3.6 mW from a single 0.9-V supply. The design shows very good robustness across different tested samples, supply variations, and across temperatures from −20 °C to 80 °C.

A 0.00426 mm2 77.6-dB Dynamic Range VCO-Based CTDSM for Multi-Channel Neural Recording

Driven by needs in neuroscientific research, future neural interface technologies demand integrated circuits that can record a large number of channels of neural signals in parallel while maintaining a miniaturized physical form factor. Using conventional methods, it is challenging to reduce circuit area while maintaining the high dynamic range, low noise, and low power consumption required in the neural application. This paper proposes to address this challenge using a VCO-based continuous-time delta-sigma modulator (CTDSM) circuit, which can record and digitize neural signals directly without the need for front-end instrumentation amplifiers and anti-aliasing filters, which are limited by the abovementioned circuit-area performance tradeoff. Thanks to the multi-level quantization and intrinsic mismatch-shaping capabilities of the VCO-based approach, the proposed first-order CTDSM can achieve comparable electrical performance to a higher-order CTDSM while offering further area and power reductions. We prototyped the circuit in a 22-channel test chip and demonstrate, based on the chip measurement results, that the proposed modulator occupies an area of 0.00426 mm2 while achieving input-referred noise levels of 6.26 and 3.54 µVrms in the action potential (AP) and local field potential (LFP) bands, respectively. With a 77.6 dB wide-dynamic range, the noise and total harmonic distortion meet the requirements of a neural interface with up to 149 mVpp input AC amplitude or up to ±68 mV DC offsets. We also validated the feasibility of the circuit for multi-channel recording applications by examining the impact of cross-channel VCO oscillation interferences on the circuit noise performance. The experimental results demonstrate the proposed architecture is an excellent candidate to implement future multi-channel neural-recording interfaces.

Correlated Dual-Loop Sturdy MASH Continuous-Time Delta-Sigma Modulators

This article presents a new multi-loop delta-sigma modulator (DSM) structure that combines the advantages of both the traditional multi-stage noise shaping (MASH) and sturdy MASH (SMASH) architectures. It removes the need for an explicit quantization error extraction digital-to-analog converter (DAC) typically required in multi-loop structures, which allows to eliminate the delay mismatch problem related to the intrinsic propagation delay of the first loop quantizer. The proposed architecture essentially uses the SMASH architecture as its core and has similar characteristics. However, it further simplifies the structure allowing to remove all the feedback DACs in the cascaded loop. The prototype DSM fabricated in a 65-nm process achieves signal-to-noise-and-distortion ratio (SNDR) and dynamic range (DR) of 73.4 and 78.3 dB, respectively, in an 18.75-MHz bandwidth. With 1.1/1.5-V (1.5 V for DAC) supply voltage, the prototype DSM consumes 17.85 mW at 600-MHz operating speed corresponding to a Walden and Schreier figure of merits (FOMs) of 124.1 fJ/conv-step and 168.6 dB (using DR result), respectively.