Delay-locked Loop Research Articles

A Cascade Fractional-N Synthesizer Topology of DLL and Frequency Multiplier for 5G+ Communication Systems

This study presents a synthesizer topology based on a delay-locked loop (DLL) and programmable frequency multiplier for 5G+ communication systems. The proposed synthesizer comprises a 512-phase DLL, an intermediate frequency generator (IFG), and an RF frequency multiplier (RFFM). The 512-phase DLL provides 512 delayed pulses through a chain of 256 delay units and single-to-differential complementary converters (S2DCs). The IFG comprises I/Q-multiplexers, I/Q-accumulators, an XOR, and an S2DC. The I/Q-multiplexer outputs switch to the phase lag or lead waveforms at every rising or falling edge of the outputs, which makes the I/Q-multiplexer output frequency, fMX, programmable. The IF, fIF, is two times fMX, and fIF is up-converted to RF, fRF, through the RFFM. When the reference clock frequency, fref, is 156.25 MHz, the fIF range is 156.863–312.5 MHz and the fRF dynamic range is approximately 1.89–9.96 GHz. The channel resolution range is 3.698–38.609 MHz. Consequently, the proposed synthesizer provides a wide 134% output frequency bandwidth and a finer channel resolution smaller than fref. The presented synthesizer is fabricated in a 65 nm CMOS process. The total power consumption is 15 mW, and the rms jitter integrated from 1 kHz to 100 MHz measured as 107.6 fs.

Leveraging machine learning for the detection of structured interference in Global Navigation Satellite Systems

Radio frequency interference disrupts services offered by Global Navigation Satellite Systems (GNSS). Spoofing is the transmission of structured interference signals intended to deceive GNSS location and timing services. The identification of spoofing is vital, especially for safety-of-life aviation services, since the receiver is unaware of counterfeit signals. Although numerous spoofing detection and mitigation techniques have been developed, spoofing attacks are becoming more sophisticated, limiting most of these methods. This study explores the application of machine learning techniques for discerning authentic signals from counterfeit ones. The investigation particularly focuses on the secure code estimation and replay (SCER) spoofing attack, one of the most challenging type of spoofing attacks, ds8 scenario of the Texas Spoofing Test Battery (TEXBAT) dataset. The proposed framework uses tracking data from delay lock loop correlators as intrinsic features to train four distinct machine learning (ML) models: logistic regression, support vector machines (SVM) classifier, K-nearest neighbors (KNN), and decision tree. The models are trained employing a random six-fold cross-validation methodology. It can be observed that both logistic regression and SVM can detect spoofing with a mean F1-score of 94%. However, logistic regression provides 165dB gain in terms of time efficiency as compared to SVM and 3 better than decision tree-based classifier. These performance metrics as well as receiver operating characteristic curve analysis make logistic regression the desirable approach for identifying SCER structured interference.

A 16-bit 18-MSPS flash-assisted SAR ADC with hybrid synchronous and asynchronous control logic

This paper presents a 16-bit, 18-MSPS (million samples per second) flash-assisted successive-approximation-register (SAR) analog-to-digital converter (ADC) utilizing hybrid synchronous and asynchronous (HYSAS) timing control logic based on an on-chip delay-locked loop (DLL). The HYSAS scheme can provide a longer settling time for the capacitive digital-to-analog converter (CDAC) than the synchronous and asynchronous SAR ADC. Therefore, the issue of incomplete settling or ringing in the DAC voltage for cases of either on-chip or off-chip reference voltage can be solved to a large extent. In addition, the foreground calibration of the CDAC’s mismatch is performed with a finite-impulse-response bandpass filter (FIR-BPF) based least-mean-square (LMS) algorithm in an off-chip FPGA (field programmable gate array). Fabricated in 40-nm CMOS process, the prototype ADC achieves 94.02-dB spurious-free dynamic range (SFDR), and 75.98-dB signal-to-noise-and-distortion ratio (SNDR) for a 2.88-MHz input under 18-MSPS sampling rate.

A shared TDC-based fast-lock all-digital DLL using a DCC-embedded delay line

A novel shared time-to-digital converter (TDC)-based, fast-locking, all-digital delay-locked loop (DLL) incorporating a duty-cycle corrector (DCC)-embedded delay line is introduced. The proposed DLL employs a shared TDC-based structure for both phase locking and duty-cycle correction operations, enabling rapid lock times of approximately 22 clock cycles. The proposed DLL offers the benefit of resolving the delay mismatch issue and achieving a rapid lock time by utilizing a shared delay line structure for both the TDC and the DCC-embedded delay line. This approach allows for high-speed operation up to 3.5 GHz. Implemented using a 65-nm 1.0-V CMOS process, the proposed DLL supports a frequency range from 0.8 to 3.5 GHz, offers a duty-cycle correction range of ±20 % at 0.8 GHz. It achieves an effective peak-to-peak output clock jitter of just 5.4 ps at 3.5 GHz, while maintaining a compact active area of 0.08 mm2 and operating with a power consumption of only 8.0 mW at 3.5 GHz.

Random forest-based multipath parameter estimation

Multipath is recognized as one of the major error sources for GNSS urban navigation. This study proposes a random forest (RF)-based multipath parameter estimator that uses random forest regression for parameter estimation, thereby mitigating multipath effect by removing the estimated reflected signal components. The proposed estimator is evaluated and compared with the multipath estimation delay-lock loop (MEDLL) for one-multipath and three-multipath cases, respectively. Simulation results demonstrate that the RF-based estimator is less affected by the front-end bandwidth of received signals, compared with MEDLL. The proposed RF-based estimator shows better performance than MEDLL for signals with front-end bandwidths of lower than 6 MHz. In 20 sets of tests on signals with a front-end bandwidth of 10 MHz in the three-multipath case, the RF-based estimator obtains smaller standard deviations than MEDLL. In experiments using real data with a front-end bandwidth of 2 MHz, the RF-based estimator reduces the 2D and 3D positioning errors by 8.5% and 8.7% over 180 epochs, respectively, against the conventional delayed-locked loop (DLL).

AstroPix4 — a novel HV-CMOS sensor developed for space based experiments

For the proposed space based gamma-ray observatory All-sky Medium-Energy Gamma-ray Observatory eXplorer (AMEGO-X), a silicon tracker based on a novel High Voltage-CMOS (HV-CMOS) sensor called AstroPix, is currently being developed. Preliminary measurements with the first full reticle prototype AstroPix3 show that the power target of 1.5 mW/cm2 can currently not be reached due to the digital consumption of 3.08 mW/cm2, while the analog power consumption of 1.04 mW/cm2 and a break down voltage of over 350 V look promising. Based on these results, the design changes in AstroPix4, submitted in May 2023, are presented, containing changes to the time stamp generation and readout architecture. A digital power consumption below 0.25 mW/cm2 is expected by removing the fast 200 MHz clock used to measure the time-over-threshold (ToT) and an LVDS receiver. A maximum resolution of 3.125 ns for time-of-arrival (ToA) and ToT is reached by adding per-pixel Flash-Time-to-Digital Converter (TDCs) controlled by a global delay-locked loop (DLL).

Anti-Multipath Underwater Acoustic Time-Delay Detection Algorithm Based on Dual-Delta Correlators

For the underwater acoustic (UAC) positioning system based on continuous waveform signal, the time-delay estimation of the Line-of-sight (Los) is not robust under the UAC strongly time-varying multipath channel. So an anti-multipath time-delay detection algorithm based on dual-delta (DD) correlators is proposed in this paper to address the issue. The algorithm uses a differential processing code-phase discriminator model to improve the traditional delay-locked-loop (DLL) time-delay detection algorithm, and combines it with the signal tracking loop adapted to the UAC channel condition to estimate time-delay. Theoretical analysis indicates that due to the reduction of local code interval and the differential processing operation, the proposed algorithm effectively mitigates the effect of time-varying multipath signals on time-delay estimation compared with conventional methods. Simulation analysis further demonstrates that the proposed algorithm can robustly detect the Los and achieve high-precision time-delay estimation under the time-varying multipath channel. The algorithm shows great potential for practical applications.

An evenly-spaced-phase all-digital DLL using dual-loop SAR control

This study introduces an all-digital delay-locked loop (ADDLL), which generates 20 evenly-spaced-phase clock signals. A successive-approximation register (SAR)-based dual-loop control is used to realize the locking process of the ADDLL. A modified SAR unit combined with a tri-state digital phase detector (TSDPD) is adopted to achieve a closed-loop operation of the ADDLL. A delay matrix, which can significantly reduce the jitter accumulation, is used to generate evenly spaced phases without using a long-cascaded delay line. Additional harmonic-lock detector circuits are added to the two control loops to avoid the harmonic lock issue. The ADDLL is designed and fabricated using a 0.18μm mixed-signal CMOS technology with an active area of 0.109 μm2. The lock range of the ADDLL is 30–230 MHz and the power consumption of the ADDLL is 8.9 mW at 100 MHz. The measured rms jitter is 23.3 ps at 100 MHz, and the results show a good linearity of the multiphase outputs at a 100 MHz input clock where the maximum DNL and INL are 0.08 and -0.22 LSB, respectively. The proposed ADDDLL is highly suitable for low-frequency, low-power, and high-time-resolution applications.

A 0.55-mm2 8-bit 32-GS/s TI-SAR ADC with optimized hierarchical sampling architecture

This paper analyzes the bandwidth of the time-interleaved analog-to-digital converter (TI-ADC) with hierarchical sampling and presents an 8-bit 32-GS/s TI-ADC in 28-nm CMOS. The front-end sampler is implemented by a two-stage hierarchical sampling architecture to extend the analog input bandwidth. The 32-way sub-ADCs are realized with 2b/cycle successive approximation register (SAR) architecture and non-binary search strategy, which meet the requirements of high speed, medium resolution, and strong robustness. Multi-phase low-jitter clock tree is designed based on the delay-locked loop (DLL). Calibration methods for timing skew, offset and gain mismatches are introduced to improve accuracy. The proposed TI-SAR ADC achieves an analog input bandwidth of 23.7 GHz. It occupies an active area of 0.55 mm2 and consumes 356 mW at 1.8/1 V supply.

An Ultrasonic Transceiver for Non-Invasive Intracranial Pressure Sensing.

This paper presents a 9-mW ultrasonic through-transmission transceiver (TRX) for portable, non-invasive intracranial pressure (ICP) sensing. It employs two ultrasound transducers placed at the temporal bone windows to measure changes in the ultrasonic time-of-flight (ToF), based on which the skull expansion and the corresponding ICP waveform are derived. Key components include a high-efficiency Class-DE power amplifier (PA) with 95% efficiency and an output swing of 15.8 VPP, along with a successive approximation register (SAR) delay-locked loop (DLL)-based time-to-digital converter (TDC) with 29.8 ps resolution and 122 ns range. Other than electrical characterization, the sensor is validated through two demonstrations using a water tank setup and a human head phantom setup, respectively. It demonstrates a high correlation of R2 = 0.93 with a medical-grade invasive ICP sensor. The proposed system offers high accuracy, low power consumption, and reliable performance, making it a promising solution for real-time, portable, non-invasive ICP monitoring in various clinical settings.

A Gradient-Gated SPAD Array for Non-Line-of-Sight Imaging

Time-resolved non-line-of-sight (NLOS) imaging based on single-photon avalanche diode (SPAD) detectors have demonstrated impressive results in recent years. To acquire adequate number of indirect photons from a hidden scene in the presence of overwhelming amount of early-arrival photons, a single-gated SPAD is widely employed to mitigate pile-up. However, additional prior knowledge of the hidden range and relay surface profile are required to preset the gating position and implement the reconstruction. With this work, we propose a gradient-gated technique to alleviate these shortcomings (pile-up and prior knowledge) in NLOS imaging with the development of a 6 × 6 SPAD array fabricated in a standard 55-nm Bipolar-CMOS-DMOS (BCD) technology. The SPAD sensor includes a delay-locked loop (DLL) block, a gating generator and a pixel array, which can be flexibly configured to free-running, single-gating and gradient-gating modes. The rise time of the gates is less than 450 ps (from 10% to 90%). In gradient-gating mode, the interval time between adjacent gates can be configured from 300 ps to 2 ns. In single-gating mode, the minimum gate window is measured below 5 ns. We demonstrated the sensor in a confocal NLOS imaging system that reconstructs hidden scenes with both retroreflective and diffuse objects. The presented scheme enables the development of calibration-free NLOS imaging modality for practical applications.

A Check-and-Balance Scheme in Multiphase Delay-Locked Loop

A Check-and-Balance Scheme in Multiphase Delay-Locked Loop

Design of a Low-Power Delay-Locked Loop-Based 8× Frequency Multiplier in 22 nm FDSOI

A low-power delay-locked loop (DLL)-based frequency multiplier is presented. The multiplier is designed in 22 nm FDSOI and achieves 8× multiplication. The proposed DLL uses a new simple duty cycle correction circuit and is XOR logic-based for frequency multiplication. Current starved delay cells are used to make the circuit power efficient. The circuit uses three 2× stages instead of an edge combiner to achieve 8× multiplication, thus requiring far less power and chip area as compared to conventional phase-locked loop (PLL) circuits. The proposed 8× multiplier occupies an active area of 0.09 mm2. The measurement result shows ultra-low power consumption of 130 µW at 0.8 V supply. The post-layout simulation shows a timing jitter of 24 ps (pk-pk) at 2.44 GHz.

Analysis of the transient dose rate effect on clock resources of JXCV5SX95T FPGA

This paper qualitatively investigates the transient dose rate effect (TDRE) on clock resources of the JXCV5SX95T FPGA, including DLL (Delay Locked Loop), PLL (Phase Locked Loop), and GCB (General Clock Buffer). Our previous experimental results showed that the sensitivity of different clock resources in the JXCV5SX95T FPGA presents prominent discrepancies. In particular, all input/outputs (IOs) present a simultaneous glitch during irradiations. And, the DLL and PLL would appear special short interrupt failures in some cases. However, the experimental results lack a mechanism analysis. In order to investigate the intrinsic mechanisms and in particular to compare the sensitivity differences between the PLL and DLL circuits, corresponding TCAD and SPICE simulations are performed. Both relevant DLL and PLL circuits are established in the SPICE simulator. The radiation-induced photocurrents are calculated by TCAD, and introduced into SPICE simulations. First, with an ideal power supply, the radiation performances of the DLL and PLL are simulated, and the influence of two factors are analyzed, including the substrate size of the TCAD model and the charge pump type of the DLL and PLL. Second, typical non-ideal power supply and IO models are used in the simulations. Simulation results indicate that the short interrupt of the PLL and DLL in experiments should result from the relevant power regulators in the FPGA. Last, piecewise linear voltage sources are applied to simulate the noise on the power supply in experiments, and their influence on the PLL, DLL, IOs are analyzed. Simulation results show that the simultaneous glitch in experiments may be mainly from the power supply noise, and the radiation effect of IOs would also contribute to this failure to some degree.

A Fast-Lock Variable-Gain TDC-Based N/M-Ratio MDLL Clock Multiplier

A variable-gain time-to-digital converter (TDC)-based multiplying delay-locked loop (MDLL) clock multiplier featuring fast-locking and programmable N/M-ratio frequency multiplication capability is presented in this paper. The proposed all-digital programmable N/M-ratio MDLL achieves fast-locking capability by adopting a new variable-gain TDC. In conventional fixed-gain TDC-based MDLLs, the lock time increases as the value of the multiplication factor N decreases. However, the proposed variable-gain TDC can minimize the MDLL lock time by adjusting the TDC gain according to the change in N value. Implemented in a 40 nm 1.1-V CMOS process, the proposed all-digital MDLL clock multiplier generates output clock frequencies ranging from 0.65 to 3.2 GHz, with programmable N/M ratios of N = 5 to 16 and M = 1 to 8. It achieves a fast lock time of only 3 × M (=9) reference clock cycles when N/M = 10/3 at 2.0 GHz and demonstrates a simulated peak-to-peak jitter of 3.16 ps at 3.2 GHz when N/M = 16/3. Additionally, it occupies an active area of only 0.02 mm2 (=200 μm × 100 μm) and consumes a power of 2.3 mW at 1.0 GHz.

Dead-Zone Free, Static Phase Offset Improvement Phase Detector for High Resolution and Low Jitter Delay-Locked Loop

This work presents a phase detector (PD) having dead-zone free and static phase offset improvement performance. The proposed phase detector inherits the low power consumption advantage of the conventional phase detector using two true-single-phase clocking (TSPC) DFFs. It also effectively reduces the static phase offset, even in the presence of inevitable charge pump current mismatch. And the dead-zone problem of conventional TSPC PD is overcome by using a falling edge delay inverter. The PD is implemented using a standard 180nm CMOS technology. The dimension of the PD’s layout is 11μm×16μm. Post-layout simulation shows that the power consumption is 53.8μW at 250MHz and 160μW at 800MHz. It achieves tiny static phase offset even if the charge pump has a 3.8% current mismatch.

Pseudolite Multipath Estimation Adaptive Mitigation of Vector Tracking Based on Ref-MEDLL

Among many indoor positioning technologies, pseudolite positioning technology has become an important supplement to GNSS. In indoor open environments, pseudolite positioning technology can usually perform high-precision positioning. However, in a complex environment, the pseudolite receiver is seriously interfered by multipath and other interference signals, which will lead to a serious decline in the observation accuracy, signal lock loss or even no positioning results. Therefore, this work proposes a pseudolite indoor anti-multipath receiver based on reference multipath estimating delay lock loop (Ref-MEDLL). It adds the Ref-MEDLL multipath estimator module and the multipath mitigation module to the traditional receiver signal processing architecture. In the multipath mitigation module, the multipath estimation adaptive mitigation of vector tracking (MEAM-VT) method and the multipath estimation direct mitigation (MEDM) method for multipath mitigation is proposed. Experimental results show that the Ref-MEDLL multipath estimation method has good adaptability to multipath signals that have different time delays and different amplitudes; both the MEDM receiver and the MEAM-VT receiver have good multipath mitigation performance. The MEAM-VT method performs better than the MEDM method in multipath mitigation and tracking, but the stability of the pseudorange observations of the MEAM-VT method is not as good as that of the MEDM method. The positioning accuracy of the MEDM receiver and the MEAM-VT receiver has been improved to different degrees in static positioning experiments and dynamic positioning experiments.

Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization

A Delay-Locked Loop (DLL) circuit is indispensable for clock synchronization in a chip incorporating several heterogeneous dice. It has been shown previously that a fault and soft-error tolerant DLL can be achieved by Triple-Module Redundancy (TMR) enhanced with a timing correction scheme. However, the prior work still has a severe limitation -it does not consider the latency of the clock tree, and this limitation will make it infeasible in realistic situations. We demonstrate in this paper that this limitation can be overcome by a new “clock-latency-aware” architecture, thereby making a fault and soft-error-tolerant DLL truly realistic.

Design of a Clock Doubler Based on Delay-Locked Loop in a 55 nm RF CMOS Process

In this paper, for the wireless network, wearable device, and Internet of Things (IoT) markets, a delay-locked loop (DLL) is used to implement accurate multiplication for a reference clock and the frequency of various applications through an edge combiner (EC). A simpler structure is more sensitive to process, voltage, and temperature (PVT), so DLL complements itself quickly in the feedback system and improves the stability of the final output. The proposed DLL-based multiplier can prevent harmonic lock generation using a first phase canceller (FPC), thus compensating for faster lock time. The circuit is built with a 55 nm CMOS process and has a chip area of 0.0225 mm2. The proposed design achieves a total power consumption of 0.48 mW at the 30.72 MHz operating clock frequency, and the clock duty can also operate stably from 15 to 75%.

A Design of a Dual Delay Line DLL with Wide Input Duty Cycle Range

This article describes a dual-controller dual-delay line delay lock loop (DC-DL DLL). The proposed DLL adopted a dual delay line structure, each delay line was composed of a coarse adjustment and a fine adjustment unit, and the dual delay lines had corresponding control units to reduce the mismatch between the delay lines, and it avoided the complicated design of duty cycle correction (DCC) circuit. A frequency divider was added to divide the input clock to achieve a wider input clock duty cycle adjustment. Additionally, a simple clock synthesis circuit was proposed to synthesize the required clock. The DLL design used the 25 nm process with a voltage of 1.2 V. The simulation results showed that at a working frequency of 1.6 GHz, the peak-to-peak jitter of the DC-DL DLL after locking was approximately 17.61 ps, the maximum output duty cycle error was about 1.3%, and the input duty cycle ranged from 20% to 80%, with a power consumption of 10.06 mW.