Delay-locked Loop Research Articles

A Low-Power Sensing System of VEGF Concentration With Noise Reduction Using Subsampling Technique for Cancer Diagnosis

This paper presents a monolithic low-power sensing system for early cancer detection. The system uses a CMOS MEMS capacitive transducer with a gold interdigitated electrode (IDE) and DNA aptamers to sense the concentration of vascular endothelial growth factor (VEGF). When the DNA aptamer is immobilized with the VEGF sensor, it generates an electric double-layer capacitance. The low-noise front-end circuits amplify this capacitance change and convert the signal into the frequency domain. To solve the wide input dynamic range and reduce power consumption, a two-step time-to-digital converter (TDC) is utilized. The proposed sub-sampling (SS) technique provides a higher conversion gain to reject noise interference and overcome the increase in noise floor introduced from the decoder due to lower supply voltage. The sub-sampling delay-locked loop (SSDLL), combined with the calibration circuit, enhances TDC linearity and noise performance while preventing calibration noise from degrading conversion accuracy. Finally, the time-based information is converted into digital codes with high power efficiency for early cancer analysis. The system is fabricated in TSMC 0.35 μm MEMS CMOS process with electroplated gold. Measurement results show that the power consumption of the readout circuit and the overall system is only 18 μW and 60.65 μW, respectively. The proposed system improves jitter by 49% and achieves 0.725 mV/pg-mL sensitivity.

A low-power 1 Gb/s line driver with configurable pre-emphasis for lossy transmission lines

A line driver with configurable pre-emphasis is implemented in a 65 nm CMOS process. The driver utilizes a three-tap feed-forward equalization architecture. The relative delays between the taps are selectable in increments of 1/16th of the unit interval via an 8-stage delay-locked loop and digital interpolator. It is also possible to control the output amplitude and source impedance for each tap via a programmable array of eight source-series terminated drivers. The entire design consumes 9 mW from a 1.2 V supply at 1 Gb/s.

Evaluation of Low-Complexity Adaptive Full Direct-State Kalman Filter for Robust GNSS Tracking.

This paper evaluates the implementation of a low-complexity adaptive full direct-state Kalman filter (DSKF) for robust tracking of global navigation satellite system (GNSS) signals. The full DSKF includes frequency locked loop (FLL), delay locked loop (DLL), and phase locked loop (PLL) tracking schemes. The DSKF implementation in real-time applications requires a high computational cost. Additionally, the DSKF performance decays in time-varying scenarios where the statistical distribution of the measurements changes due to noise, signal dynamics, multi-path, and non-line-of-sight effects. This study derives the full lookup table (LUT)-DSKF: a simplified full DSKF considering the steady-state convergence of the Kalman gain. Moreover, an extended version of the loop-bandwidth control algorithm (LBCA) is presented to adapt the response time of the full LUT-DSKF. This adaptive tracking technique aims to increase the synchronization robustness in time-varying scenarios. The proposed tracking architecture is implemented in an GNSS hardware receiver with an open software interface. Different configurations of the adaptive full LUT-DSKF are evaluated in simulated scenarios with different dynamics and noise cases for each implementation. The results confirm that the LBCA used in the FLL-assisted-PLL (FAP) is essential to maintain a position, velocity, and time (PVT) fix in high dynamics.

A Wide-Range Four-Phase All-Digital DLL with De-Skew Circuit

A four-phase all-digital delay-locked loop (ADDLL) with a de-skew circuit for NAND Flash high-speed interfaces is proposed. The proposed de-skew circuit adopts a fall-edge-judgment phase adjuster and a three-stage digitally controlled delay line to align the system input clock and 0∘ output clock of the four-phase DLL over a wide frequency range, thus solving the four-phase offset caused by clock skew. A parallel-cascade configuration is proposed to solve the variable phase alignment problem caused by mode switching, thus effectively improving the phase-locked accuracy. The proposed circuit is fabricated in the 0.13 μm CMOS process with a 0.072 mm2 core area. The chip testing results show an operating frequency range from 26 MHz to 1.55 GHz and a typical alignment error of approximately 17 ps.

Design and performance of a 16-channel coarse-fine TDC prototype ASIC

This paper presents a prototype of a 16-channel Time-to-Digital Converter (TDC) based on the coarse-fine architecture for a small animal Position Emission Tomography (PET) system, which achieves both a large measurement range and high precision. The coarse time stamp is provided by two 12-bit counters, and the duplication of hardware is intended to avoid metastability when the hit signal edge is close to the edge of the counter clock. The fine time stamp is realized with a tunable delay line, which is adjusted by a 32-stage Delay-Locked Loop (DLL) and provides submultiples of the counter clock period. The device has been designed and fabricated in a 180 nm CMOS process. With a 200 MHz system clock, the full-scale measurement range is 20.48μs and the fine bin size is 156 ps. The test results show that the differential nonlinearity (DNL) is between −0.2 to ＋0.2 LSB, and the and integral nonlinearity (INL) is within the range of −0.5 to 0.2 LSB for all 16 channels. The one-shot time precision is better than 60 ps RMS. Power consumption of each channel is less than 8 mW.

A 12-Bit 1-GS/s Pipelined ADC with a Novel Timing Strategy in 40-nm CMOS Process

This paper presents a 1-GS/s12-bit pipelined analog-to-digital converter (ADC) fabricated in 40-nm CMOS technology that optimizes the settling time, bit error rate, and robustness. This ADC uses an improved timing called pre-quantization timing (PQT), which implements quantization in half the time of the sampling phase to maximize the output-settling time of the operational amplifier (op-amp). A complete clocking scheme along with a delay lock loop (DLL) is proposed to generate an accurate timing no matter how process, voltage, and temperature (PVT) change. Based on PQT, a high-speed comparator circuit is adopted to obtain a bit error rate (BER) below 10−15. Sample and hold amplifier (SHA) is used to guarantee robustness over the wide input frequency. Furthermore, a low-cost automatic calibration is implemented to correct residual curves, and inter-stage gain errors are also corrected. This ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.3 dB and a spurious-free dynamic range (SFDR) of 78.5 dB at a 227 MHz input frequency. The measured differential nonlinearities (DNL) and integral nonlinearities (INL) after calibration are ±0.7 LSB and ±1.50 LSB, respectively. The power consumption of the ADC core is 97.6-mW, and the Walden figure of merit (FoM) is 172.9-fJ/conversion-step.

Multipath Mitigation for BOC Signals Based on Prompt-Assisted-Offset Correlator

Tracking ambiguity and multipath are two serious threats in processing binary offset carrier (BOC) signals that are widely used in global navigation satellite systems (GNSS). Three-loop tracking methods, such as dual binary phase-shift keying tracking (DBT), use a delay lock loop (DLL), a phase lock loop (PLL), and a subcarrier PLL (SPLL) to track the code, carrier, and subcarrier, respectively, thus solving the tracking ambiguity problem. However, the multipath remains an important factor in the ranging performance deterioration of these tracking methods. Using the offset correlator (OC) technique in the SPLL can effectively mitigate subcarrier multipath errors, but it substantially raises thermal noise errors. To solve this contradiction, this paper proposes a prompt-assisted-offset correlator (PAOC) technique that combines the prompt and offset correlators in a complementary way to mitigate multipath for BOC signals. Compared with the original OC technique, the PAOC technique has less thermal noise performance loss. Moreover, this paper discovers and quantifies the interaction between carrier and subcarrier multipath errors by analyzing the coupling effect between SPLL and PLL. Most multipath mitigation methods for BOC signals ignore the carrier multipath in the PLL, so their subcarrier multipath performance is not optimal. Thus, this paper further proposes applying the PAOC technique in both PLL and SPLL to mitigate carrier and subcarrier multipath errors simultaneously. Theoretical analysis and experimental results demonstrate that the proposed method can significantly improve the multipath performance with small noise performance loss.

A Low-Phase-Noise Self-Aligned Sub-Harmonically Injection-Locked PLL Using Aperture Phase Detector-Based DLL Windowing Technique

This paper proposes a self-aligned sub-harmonically injection locked phase locked loop (SILPLL) in 180-nm Semi Conductor Laboratory (SCL) CMOS technology. In this work, an aperture phase detector (APD) based delay locked loop (DLL) with windowing technique is proposed to dynamically align the injection timing of pulse with the rising edge of sub-harmonically injection locked voltage controlled oscillator. In contrast to classical self-aligned SILPLL, this work replaces the commonly deployed tri-state based phase frequency detector (PFD) in DLL by an APD, which becomes active over a pulse-window. The APD deployed in DLL reduces the in-band phase noise due to the charge pump by 12 dBc at 200 KHz offset in comparison with the classical self-aligned DLL. A detailed mathematical model of the self-aligned injection with noise sources is presented for the proposed architecture. Additionally, this work includes noise analysis with the effect of different design aspects such as locking range, and realignment factor. The proposed architecture operates at 1.8 GHz output frequency, and the simulated phase noise is −120.6 dBc/Hz at 1 MHz offset with an integrated root-mean-square jitter of 0.96 ps from 10 kHz to 30 MHz. The implemented PLL consumes 6.6 mW from 1.8 V power supply.

A 14 GHZ DELAY LOCKED LOOP WITH MINIMIZED PERIOD DELAY ERROR AND WORST 1.5% DUTY CYCLE ERROR

In many applications, the Delay Locked Loop (DLL) is used to improve the timing margin for better performance of the synchronous system. A precise 50′ duty ratio of the clock signal is essential to the DDR SDRAM, which needs both the rising edge and the falling edge of the clock to sample the data. The duty mismatch of the output clock in the DLL may be caused by the duty error of the external input clock or by the common mode voltage offset in the voltage-controlled delay line (VCDL). Many studies have presented the duty cycle corrector (DCC) to reduce the duty mismatch of the clock. This paper proposes a high-frequency DLL that generates multiplate clocks with a wide frequency range. The object of this research is to have +-1.5% duty cycle error at the output clock and, in locked state, less than 2% of clock period delay between 0- and 360-degree phases (delay error). This generator produces 8 phases at 14 GHz.

A high-resolution clock phase shifter circuitry for ALTIROC

A high-resolution clock phase shifter is implemented to adjust the phase of multiple clocks at 40 MHz, 80 MHz, or 640 MHz in the ALTIROC chip. The phase shifter has a coarse-phase shifter and a fine-phase shifter to achieve a step size of 97.7 ps and an adjustable range of 25 ns. The fine delay unit is based on a Delay Locked Loop (DLL) operating at 640 MHz. The phase shifter is fabricated in a 130 nm CMOS process. The area of the phase shifter is 725 µm × 248 µm. The Differential Non-Linearity (DNL) and the Integral Non-Linearity (INL) are ±0.6 LSB and ±0.75 LSB, respectively. The jitter from −25 °C to 20 °C is less than 15.5 ps (RMS), including the contributions from the FPGA clock source and the PLL. The power consumption is 11.2 mW.

A High-Frequency and Low-Jitter DLL With Quadrature Error and Duty-Cycle Corrections Based on Asynchronous Sampling

This paper presents a quadrature error and duty-cycle correction circuit based on an asynchronous sampling technique. Sampling the multi-phased clocks provides their phase and duty-cycle information, which are then utilized to compensate for the quadrature and duty-cycle errors. The intrinsic down-conversion operation of the proposed sampling approach enhances the correction accuracy by mitigating circuit mismatch effects. The quadrature-error corrector (QEC) and duty-cycle corrector (DCC) circuits receive control signals generated from the asynchronous phase detectors and correct the clock outputs accordingly. Combined with a delay-locked loop (DLL), the proposed design is fabricated in a 40-nm CMOS process, consumes 7.2 mW, and occupies 0.023 mm. It achieves 0.837-ps RMS jitter and 1.68∘ maximum phase error from multiple chip samples.

Two-Step Unbiased Estimation on Small-Delay Multipath of GNSS Signals Based on S-Curve Bias

Multipath error is among the main error sources of global navigation satellite systems (GNSSs). The traditional estimation method represented by the multipath estimating delay-locked loop (MEDLL) has difficulty in distinguishing small-delay multipath signals and noise during iterations, which leads to a bias in the estimation of small-delay multipath signals. To mitigate this small-delay multipath estimation bias, a two-step unbiased estimation method based on the S-curve bias (SCB) is proposed. First, the relationship among SCB, multipath parameters, and correlation spacing is derived. Second, a search approach based on the least squares is designed to obtain the turning point position of the SCB results with different correlation spacings. Third, the multipath delay can be estimated through the turning point of the SCB results. Finally, the phase and amplitude ratio of the direct signal and multipath signals is estimated by the SCB results of local carrier signal replicas with different phases. The proposed method does not contain iteration steps, which minimizes the accuracy influence introduced by the iterations. Simulations using the Spirent simulator and real signal experiment results show that the proposed algorithm can reduce the small-delay multipath error effectively with low computational complexity. Compared with MEDLL, Teager and Kaiser-MEDLL (TK-MEDLL), and high-resolution correlator (HRC) algorithms, the small-delay multipath mitigation performance of the proposed algorithm was improved by approximately 82.9%, 74.5%, and 91.7%, respectively. Therefore, the proposed algorithm can mitigate estimation bias in small-delay multipath signals effectively. This method provides a new strategy for the parametric estimation of the multipath signals of GNSS.

Study on Low-jitter and Low-power PLL Architectures for Mobile Audio Systems

This paper compares four phase-locked loops (PLLs) for mobile audio applications. We compare and analyze PLL structures and discuss the optimized PLL structure in the audio band frequency. A charge-pump-based integer-N PLL (NPLL) is employed as a reference. To improve the jitter performances, multiplying delay-locked loop (MDLL), sub-sampling PLL (SSPLL), and reference-sampling PLL (RSPLL) are employed and analyzed. The frequency range of the PLLs is from 8 MHz to 71.5 MHz. These PLL chips are fabricated using a Samsung 0.13-μm CMOS process. The resulting figures-of-merit for the NPLL, MDLL, SSPLL, and RSPLL are -204.3, -211.07, -220.29, and -213.32 dB, respectively, at 24.576 MHz. The total power consumption from a 1.5-V supply voltage is 1.82, 1.35, 1.43, and 1.64 mW, respectively.

A Cost-Effective and Compact All-Digital Dual-Loop Jitter Attenuator for Built-Off-Test Applications

A compact and low-power all-digital CMOS dual-loop jitter attenuator (DJA) for low-cost built-off-test (BOT) applications such as parallel multi-DUT testing is presented. The proposed DJA adopts a new digital phase interpolator (PI)-based clock recovery (CR) loop with an adaptive decimation filter (ADF) function to remove the jitter and phase noise of the input clock, and generate a phase-aligned clean output clock. In addition, by adopting an all-digital multi-phase multiplying delay-locked loop (MDLL), eight low-jitter evenly spaced reference clocks that are required for the PI are generated. In the proposed DJA, both the MDLL and PI-based CR are first-order systems, and so this DJA has the advantage of high system stability. In addition, the proposed DJA has the benefit of a wide operating frequency range, unlike general PLL-based jitter attenuators that have a narrow frequency range and a jitter peaking problem. Implemented in a 40 nm 0.9 V CMOS process, the proposed DJA generates cleaned programmable output clock frequencies from 2.4 to 4.7 GHz. Furthermore, it achieves a peak-to-peak and RMS jitter attenuation of –25.6 dB and –32.6 dB, respectively, at 2.4 GHz. In addition, it occupies an active area of only 0.0257 mm2 and consumes a power of 7.41 mW at 2.4 GHz.

A Dual-Phase Center-Aligned 7-Bit Digital Pulsewidth Modulator for Polar Transmitters

This article presents a dual-phase center-aligned 7-bit digital pulsewidth modulator for the envelope modulation of pulse-modulated polar transmitters (PMPTs). The digital pulsewidth modulator operates at a clock frequency and delivers the modulation frequency of 100 MHz. A delay-locked loop (DLL) consisting of 128 delay cells is used to generate the pulse edges for synthesis of center-aligned pulsewidth modulation (PWM) waveforms. The pulsewidth resolution is 78.1 ps. The measurement results show that the integral nonlinearity (INL) and differential nonlinearity (DNL) of the output pulses are within ±0.4 and ±0.3 LSB, respectively, in the duty cycle range of 2.12%–96.51%. Tested with a 20-MHz 256-quadrature-amplitude modulation (QAM) 5G new radio (NR) signal, the transmitter signal using the output of the modulator achieves the adjacent channel leakage ratio (ACLR) of −33.8 dBc.

A Waveform Sampling Prototype ASIC for Picosecond-Level Time Measurement

This article presents the design and test results of a waveform sampling application-specific integrated circuit (ASIC) based on the switched capacitor array (SCA). It integrates eight differential-input channels, and each channel consists of a 256-cell capacitor array, 256 12-bit Wilkinson analog-to-digital converters (ADCs), and a serial data readout. A sampling rate of up to 5 Gsps is achieved with a low-jitter delay-locked loop (DLL). Two shared coarse counters running at the rising and falling edges of the reference clock are used to extend the time measurement range. Several crosstalk reduction strategies were adopted in the circuit design, especially in the clock generation circuit and the digitization circuit. The ASIC has been fabricated in 180-nm CMOS process. The test results show that the random noise is approximately 0.7-mV rms after the fixed-pattern noise correction and that the precision of waveform timing is better than 7-ps rms with the sampling interval correction.

A Radiation-Hardened Delay-Locked Loop Applied for Multiple Frequency Ranges

A radiation-hardened delay-locked loop (DLL) applied for multiple frequency ranges is proposed in this paper. Novel and effective radiation-hardened techniques are applied in charge pump (CP) and voltage-controlled delay line (VCDL) to avoid inverted lock error and missing pulses error caused by single-event transient (SET). In order to ensure a wide operation frequency range, a frequency detection module is designed to detect the frequency of input signals and adjust the current source array of VCDL so as to change its delay time. Besides, an accelerate module is designed to reduce the lock time of DLL by providing an extra discharge current. According to the simulation results, the proposed DLL shows good performance when ion strikes occur and can work properly in a wide operation frequency range from 3.7[Formula: see text]GHz to 7.4[Formula: see text]GHz. Also, the proposed accelerate module helps to reduce lock time by 22.2%.

Multipath tracking with LTE signals for accurate TOA estimation in the application of indoor positioning

ABSTRACT Indoor positioning with high accuracy plays an important role in different application scenarios. As a widely used mobile communication signal, the Long-Term Evolution (LTE) network can be well received in indoor and outdoor environments. This article studies a method of using different reference signals in the LTE downlink for carrier phase time of arrival (TOA) estimation. Specifically, a solution is proposed and a multipath tracking Software Defined Receiver (SDR) is developed for indoor positioning. With our SDR indoor positioning system, the pilot signals of the LTE signals are firstly obtained by the coarse synchronization and demodulation. Then, with the assistance of the pilot signals, the time delay acquisition, the multipath estimating delay lock loop (MEDLL) algorithm, and the multipath anomaly detection are sequentially carried out to obtain navigation observations of received signals. Furthermore, to compare the performance of different pilot signals, the Secondary Synchronous Signals (SSS) and Cell Reference Signals (CRS) are used as pilot signals for carrier phase-based TOA estimation, respectively. Finally, to quantify the accuracy of our multipath tracking SDR, indoor field tests are carried out in a conference environment, where an LTE base station is installed for commercial use. Our test results based on CRS show that, in the static test scenarios, the TOA accuracy measured by the 1-σ error interval is about 0.5 m, while in the mobile environment, the probability of range accuracy within 1.0 m is 95%.

Multipath Mitigation Methods of BOC-Family Signals Based on Dual BPSK Tracking Techniques

It is well known that for binary offset carrier (BOC) signals the notorious ambiguity problem due to the multipeaked autocorrelation function must be tackled first in order to obtain the potential of improving ranging performance promised by its broader Gabor bandwidth. The existence of multipath makes it more difficult to solve. Dual binary phase-shift keying (BPSK) tracking (DBT) is a kind of low complexity, unambiguous tracking method for BOC-family signals, which makes full use of the coherence between the upper and lower sidebands and employs subcarrier phase locked loop (SLL) and delay locked loop (DLL) to track subcarrier and code components, respectively. Considering that the thermal noise performance of DBT has been fully studied, this article focuses on the analysis of multipath performance and the design of antimultipath methods under DBT framework. The influence of multipath on SLL and DLL of DBT is analyzed first and the corresponding subcarrier and code multipath error envelopes are obtained. Then according to different requirements of subcarrier and code multipath errors, a multipath mitigation scheme specially designed for DBT is proposed, in which SLL and DLL adopt offset correlator and narrow correlation, respectively. Theoretical analysis and simulation are given to verify the effectiveness of the proposed methods.

5 Gs/s 등가 시간 샘플링을 통한 K-Band UWB 레이다 송수신기

In this paper, a K-band complementary metal-oxide-semiconductor (CMOS) ultra-wide-band (UWB) radar is presented. Using an equivalent time sampling technique with a delay-locked loop (DLL), virtual 5 Gs/s high-speed sampling is implemented without using a high-speed analog–digital converter. The receiver comprises a low-noise amplifier, radiofrequency variable amplifier, mixer, and baseband analog, whereas the transmitter comprises switching and driver amplifiers. For the UWB signal, a voltage-controlled oscillator-based impulse generator provides a periodic pulse signal using a switching amplifier controlled by a DLL clock. The proposed UWB radar SoC is fabricated using a 65 nm CMOS wafer, and the measured conversion gain and noise figure of the radar receiver are 79 dB and 7.4 dB, respectively, at 24 GHz. Consequently, we confirm that the measurement of the 11.3 m standard sphere is feasible.